• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.1
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• pp.135-141
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• 2018

In this paper, we describe design and implementation of optimal smart home control system. Recent developments in technologies such as sensors and communication have enabled the Internet of Things to control a wide range of objects, such as light bulbs, socket-outlet, or clothing. Many businesses rely on the launch of collaborative services between them. However, traditional IoT systems often support a single protocol, although data is transmitted across multiple protocols for end-to-end devices. In addition, depending on the manufacturer of the Internet of things, there is a dedicated application and it has a high degree of complexity in registering and controlling different IoT devices for the internet of things. ARIoT system, special marking points and edge extraction techniques are used to detect objects, but there are relatively low deviations depending on the sampling data. The proposed system implements an IoT gateway of object based on OneM2M to compensate for existing problems. It supports diverse protocols of end to end devices and supported them with a single application. In addition, devices were learned by using deep learning in the artificial intelligence field and improved object recognition of existing systems by inference and detection, reducing the deviation of recognition rates.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.33-44
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• 2011

In this paper, we presents a hybrid on-chip bus architecture based on the AMBA 3.0 AXI protocol for MPSoC with high performance and low power. Among AXI channels, data channels with a lot of traffic are designed by crossbar-switch architecture for massively parallel processing. On the other hand, addressing and write-response channels having a few of traffic is handled by shared-bus architecture due to the overheads of (areas, interconnection wires and power consumption) reduction. In experiments, the comparisons are carried out in terms of time, space and power domains for the verification of proposed hybrid on-chip bus architecture. For $16{\times}16$ bus configuration, the hybrid on-chip bus architecture has almost similar performance in time domain with respect to crossbar on-chip bus architecture, as the masters's latency is differenced about 9% and the total execution time is only about 4%. Furthermore, the hybrid on-chip bus architecture is very effective on the overhead reduction, such as it reduced about 47% of areas, and about 52% of interconnection wires, as well as about 66% of dynamic power consumption. Thus, the presented hybrid on-chip bus architecture is shown to be very effective for the MPSoC interconnection design aiming at high performance and low power.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.74-85
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• 2015

PCI Express is a well-known and widely used de-facto system bus standard for connecting among a processor and IO devices. PCI Express is originated from old PCI standard, and its most of applications are limited to be used within a PC or server system. But, because of its fast speed, low power consumption, and good protocol efficiency, it is considered as one of a good candidate for an alternate system interconnect for many years. In this paper, we present design, implementation and early evaluation of an alternate system interconnect by utilizing PCI Express. The developed alternate system interconnect using PCI Express (named PCIeLINK) utilizes non-transparent bridging (NTB) technic which generally used in fail-over system in PCI and PCI Express. By using NTB technic, PCI Express device can be extended to outside of a system without electrical and logical problems arising during system boot and enumeration. To build up an alternate system interconnect, we designed and implemented a network interface card having multiple PCI Express ${\times}4$ connections (theoretically 20 Gbps) and tested, The early test results revealed that an ${\times}4$ port in the card showed 8.6 Gbps peak performance for bulk transmission and 5.1 Gbps peak for normal TCP/IP transfer.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.274-280
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• 2011

Due to their rapid growth and new paradigm applications, wireless sensor networks(WSNs) are morphing into low power personal area networks(LoWPANs), which are envisioned to grow radically. The fragmentation and reassembly of IP data packet is one of the most important function in the 6LoWPAN based communication between Internet and wireless sensor network. However, since the 6LoWPAN data unit size is 102 byte for IPv6 MTU size is 1200 byte, it increases the number of fragmentation and reassembly. In order to reduce the number of fragmentation and reassembly, this paper presents a new scheme that can be applicable to 6LoWPAN. When a fragmented packet header is constructed, we can have more space for data. This is because we use 8-bits routing table ill instead of 16-bits or 54-bits MAC address to decide the destination node. Analysis shows that our design has roughly 7% or 22% less transmission number of fragmented packets, depending on MAC address size(16-bits or 54-bits), compared with the previously proposed scheme in RFC4944. The reduced fragmented packet transmission means a low power consumption since the packet transmission is the very high power function in wireless sensor networks. Therefore the presented fragmented transmission scheme is well suited for low-power wireless sensor networks.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.2
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• pp.70-75
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• 2014

Recently, the demand for high-integrated, low-powered, and high-powered SoC design has been increasing due to the multi-functionality and the miniaturization of digital devices and the high capacity of service informations. With the rapid evolution of the system, the required hardware performances have become diversified, the FPGA system has been increasingly adopted for the rapid verification, and SoC system using the FPGA and the ARM core for control has been growingly chosen. While the AXI bus is used in these kinds of systems in various ways, it is traditionally designed with AXI slave structure. In slave structure, there are problems with the CPU resources because CPU is continually involved in the data transfer and can't be used in other jobs, and with the decreased transmission efficiency because the time not used of AXI bus beomes longer. In this paper, an efficient AXI master interface is proposed to solve this problem. The simulation results show that the proposed system achieves reductions in the consumption clock by an average of 51.99% and in the slice by 31% and that the maximum operating frequency is increased to 107.84MHz by about 140%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1077-1087
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• 2003

In this paper, we proposed an architecture of a cryptosystem with various operating modes for the network security and implemented in hardware using the ASIC library. For configuring a cryptosystem, the standard block ciphers such as AES, SEED and 3DES were included. And the implemented cryptosystem can encrypt and decrypt the data in real time through the wired/wireless network with the minimum latency time (minimum 64 clocks, maximum 256 clocks). It can support CTR mode which is widely used recently as well as the conventional block cipher modes such as ECB, CBC and OFB, and operates in the multi-bit mode (64, 128, 192, and 256 bits). The implemented hardware has the expansion possibility for the other algorithms according to the network security protocol such as IPsec and the included ciphering blocks can be operated simultaneously. The self-ciphering mode and various ciphering mode can be supported by the hardware sharing and the programmable data-path. The global operation is programmed by the serial communication port and the operation is decided by the control signals decoded from the instruction by the host. The designed hardware using VHDL was synthesized with Hynix 0.25$\mu\textrm{m}$ CMOS technology and it used the about 100,000 gates. Also we could assure the stable operation in the timing simulation over 100㎒ using NC-verilog.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.5B
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• pp.512-521
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• 2003

In this paper, we introduce our experience of the design and implementation of mobile collaboration system(MCS) that support people using mobile devices to participate in cooperative session. There are considerable differences between desktop PC and mobile devices like PDA in processing ability, resolution of display and color degree. In the case of mobile devices, they use different processors and different operating system and they have even differences in ability of executing application. The mobile collaborative system based on T.120 protocol of ITU-T standard compromised of mobile collaboration server, mobile collaboration client, session node and application. We also define the session node in desktop PC in which session control block and communication block runs. This node provide functions of session control block and communication block to mobile collaboration clients and so lighten load of clients. The mobile collaboration server provides information of candidates for session node, session and user to mobile collaboration client. And this server support clients to configure their own session node and manage sessions. Only the mobile collaboration client module and applications including APE are executed in a mobile device when user using mobile devices would like to participate in cooperative session. We implemented mobile collaboration client and applications with JAVA to support platform independency.

• Korean Journal of Clinical Pharmacy
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• v.28 no.2
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• pp.146-153
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• 2018

Objective: Multi-regional clinical trials have been widely used for accelerating global drug development by multinational pharmaceutical companies. In this study, we aimed to review and analyze the international trends in regulations and guidelines on multi-regional clinical trials by regulatory authorities and international organizations, such as International Conference on Harmonisation, for referring to policies, including development of domestic guidelines for multi-regional clinical trials. Methods: The policies, regulations, and guidelines published by the US Food and Drug Administration, European Medicines Agency, Pharmaceuticals and Medical Devices Agency (Japan), and China Food and Drug Administration were searched, and the International Conference on Harmonisation E17 draft guideline was reviewed. Results: The regulatory authorities in developed countries have developed and implemented regulations and guidelines on multi-regional clinical trials to promote simultaneous global drug development and evaluate the regional differences in drug safety and efficacy. International Conference on Harmonisation developed the draft guideline for planning/designing of multi-regional clinical trials in 2016, which recommends the general principles for strategy-related issues and design of multi-regional clinical trials, and for protocol-related issues, such as consideration of regional variability, subject selection, dose selection, endpoints, comparators, overall sample size, allocation to regions, collecting information on efficacy and safety, and statistical analysis. Conclusion: It is important to understand the international regulatory requirements for designing and planning of multi-regional clinical trials for global drug development. Moreover, it is necessary to prepare multi-regional clinical trial guidelines in accordance with the Korean regulation for clinical trials and drug administration.

• The Journal of Korean Academy of Sensory Integration
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• v.15 no.2
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• pp.35-45
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• 2017

Objective : The purpose of this study is to investigate the effect of modified Interactive Metronome (IM) program which is applicable to clinical practice based on the IM protocol on the behavioral symptoms, timing and motor function of children with Attention Deficit Hyperactivity Disorder (ADHD). Method : This study used one-group pretest-posttest research design. 13 ADHD children aged 7-12 years in Busan were participated in this study. The participants were underwent 24 sessions of 30 minutes intervention, 3 times a week. Evaluations were performed before- and after the intervention. Measurements used in this study were Korean-ADHD Rating Scale for behavior symptom, Long Form Assessment (LFA) for the timing, and second version of Bruininks-Oseretsky Test of Motor Proficiency (BOT-2) for the motor function. Results : There was a significant improvement in hyperactivity / impulsivity among the behavioral symptoms, and there was a statistically significant improvement in timing, hand coordination, and body coordination. Conclusion : Modified IM program for clinical application has significant effect on improving behavioral symptoms, timing and motor function of children with ADHD.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.7
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• pp.31-40
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• 2004

In this paper, we analyze mathematically the performance of the gated service scheduling in the Interleaved Polling with Adaptive Cycle Time(IPACT) was proposed to control upstream traffic for Gigabit Ethernet-PONs. In the analysis, we model EPON MAC protocol as a polling system and use mean value analysis. We divide arrival rate λ into three regions and analyze each region accordingly In the first region in which λ value is very small, there are very few ONUs' data to be transmitted. In the second region in which λ has reasonably large value, ONUs have enough data for continuous transmission. In the third region, ONUs' buffers are always saturated with data since λ value is very large. We obtain average packet delay, average Queue size, average cycle time of the gated service. We compare analysis results with simulation to verify the accuracy of the mathematical analysis. Simulation requires much time and effort to evaluate the performance of EPONs. On the other hand, mathematical analysis can be widely used in the design of EPON systems because system designers can obtain various performance results rapidly. We can design appropriate EPON systems for varioustraffic property by adjusting control parameters.