• 제목/요약/키워드: Protection algorithm

검색결과 820건 처리시간 0.03초

다중링-메시 토폴로지 기반 T-SDN(Transport SDN)에서 보호·복구 경로 계산 방식 (Protection and restoration path calculation method in T-SDN (Transport SDN) based on multiple ring-mesh topology)

  • 김현철
    • 융합보안논문지
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    • 제23권1호
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    • pp.3-8
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    • 2023
  • 다중 도메인 광 전송망은 기본적으로 상호 운용되지 않으며 전체 망차원의 통합 오케스트레이션 메커니즘과 경로 제공 메커니즘이 필요하다. 더불어 망의 생존성 보장은 중요한 쟁점 중의 하나이다. MPLS-TP(Multi-Protocol Label Switching-Transport Profile)에서는 다양한 보호·복구 방안을 표준으로 정의하고 있으나 보호·복구 경로를 계산·선정하는 방안에 대해서는 언급하고 있지 않다. 따라서 광회선패킷 통합망 차원에서 보호·복구 충돌을 최소화하여 통합망 전 영역에 걸쳐 신속한 보호·복구가 가능한 경로를 계산·설정하는 알고리즘이 필요하다. 본 논문에서는 다중링-메시 토폴로지 형태로 구성된 T-SDN 망에서 신속한 보호·복구가 가능한 경로를 계산·설정하는 알고리즘을 제안하였다.

클라우드 컴퓨팅에서 프라이버시 보호를 지원하는 데이터 필터링 기반 병렬 영역 질의 처리 알고리즘 (Privacy-Preserving Parallel Range Query Processing Algorithm Based on Data Filtering in Cloud Computing)

  • 김형진;장재우
    • 정보처리학회논문지:컴퓨터 및 통신 시스템
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    • 제10권9호
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    • pp.243-250
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    • 2021
  • 최근 클라우드 컴퓨팅이 발전함에 따라 데이터베이스 아웃소싱에 대한 관심이 증가하고 있다. 그러나 데이터베이스를 아웃소싱하는 경우, 데이터 소유자의 정보가 내부 및 외부 공격자에게 노출되는 문제점을 지닌다. 따라서 본 논문에서는 프라이버시 보호를 지원하는 병렬 영역 질의처리 알고리즘을 제안한다. 제안하는 알고리즘은 Paillier 암호화 시스템을 사용하여 데이터 보호, 질의 보호, 접근 패턴 보호를 지원한다. 또한 기존 알고리즘에서 영역 겹침을 확인하는 프로토콜(SRO)의 연산 비용을 줄이기 위해 garbled 서킷(circuit) 을 통해 SRO 프로토콜의 효율성을 향상시킨다. 제안하는 병렬 영역질의 처리 알고리즘은 크게 2단계로 구성된다. 이는 kd-트리를 병렬적으로 탐색하고 질의를 포함하는 단말 노드의 데이터를 안전하게 추출하는 병렬 kd-트리 탐색 단계와 다수의 thread를 통해 질의 영역에 포함된 데이터를 병렬 탐색하는 병렬 데이터 탐색 단계로 구성된다. 한편, 제안하는 알고리즘은 암호화 연산 프로토콜과 인덱스 탐색의 병렬화를 통해 우수한 질의 처리 성능을 제공한다. 제안하는 병렬 영역 질의 처리 알고리즘은 thread 수에 비례하여 성능이 향상됨을 알 수 있고 10 thread 상에서 기존 기법은 38초, 제안하는 기법은 11초로 약 3.4배의 성능 향상이 있음을 보인다.

345kV 계통 모델링 데이터를 활용한 과여자 보호계전기법 (Over-Excitation Protection Relaying using the 345kV Power System Modeling Data)

  • 박철원;반우현
    • 전기학회논문지P
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    • 제60권4호
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    • pp.175-180
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    • 2011
  • A large AC generator is an important component of the power system. It is a need for research of AC generator protection relay for the next-generation ECMS and an efficient operation of protection control system. However, most of protection and control systems used in power plants have been still imported as turn-key and operated in domestic. This may cause the lack of the correct understanding on the protection systems and methods, and thus have difficulties in optimal operation. In this paper, over-excitation protection relaying is one of the protective factors in generator protection IED was presented. The cause and protection principles were dealt and, DFT-based gain compensation algorithm was adopted for the frequency measurement. The Republic of Korea 345kV modeling data by EMTP-RV was used for performance evaluation.

A Novel Shared Segment Protection Algorithm for Multicast Sessions in Mesh WDM Networks

  • Lu, Cai;Luo, Hongbin;Wang, Sheng;Li, Lemin
    • ETRI Journal
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    • 제28권3호
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    • pp.329-336
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    • 2006
  • This paper investigates the problem of protecting multicast sessions in mesh wavelength-division multiplexing (WDM) networks against single link failures, for example, a fiber cut in optical networks. First, we study the two characteristics of multicast sessions in mesh WDM networks with sparse light splitter configuration. Traditionally, a multicast tree does not contain any circles, and the first characteristic is that a multicast tree has better performance if it contains some circles. Note that a multicast tree has several branches. If a path is added between the leave nodes on different branches, the segment between them on the multicast tree is protected. Based the two characteristics, the survivable multicast sessions routing problem is formulated into an Integer Linear Programming (ILP). Then, a heuristic algorithm, named the adaptive shared segment protection (ASSP) algorithm, is proposed for multicast sessions. The ASSP algorithm need not previously identify the segments for a multicast tree. The segments are determined during the algorithm process. Comparisons are made between the ASSP and two other reported schemes, link disjoint trees (LDT) and shared disjoint paths (SDP), in terms of blocking probability and resource cost on CERNET and USNET topologies. Simulations show that the ASSP algorithm has better performance than other existing schemes.

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An Unequal Protection FEC Scheme for Video over Optical Access Networks

  • Cao, Yingying;Chen, Xue;Wang, Liqian;Li, Xicong
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제7권6호
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    • pp.1463-1479
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    • 2013
  • In this paper, we propose an unequal protection physical coding sub-layer (PCS) forward error correction (FEC) scheme for efficient and high-quality transmission of video data over optical access networks. Through identifying and resolving the unequal importance of different video frames and passing this importance information from MAC-layer to PCS, FEC scheme of PCS can be adaptive to application-layer data. Meanwhile, we jointly consider the different channel situations of optical network unit (ONU) and improve the efficiency of FEC redundancy by channel adaptation. We develop a theoretical algorithm and a hardware method to achieve efficient FEC assignment for the proposed unequal protection scheme. The theoretical FEC assignment algorithm is to obtain the optimal FEC redundancy allocation vector that results in the optimum performance index, namely frame error rate, based on the identified differential importance and channel situations. The hardware method aims at providing a realistic technical path with negligible hardware cost increment compared with the traditional FEC scheme. From the simulation results, the proposed Channel and Application-layer data Adaptation Unequal Protection (CAAUP) FEC scheme along with the FEC ratio assignment algorithm and the hardware method illustrates the ability of efficient and high-quality transmission of video data against the random errors in the channel of optical access networks.

Edge-Preserving Algorithm for Block Artifact Reduction and Its Pipelined Architecture

  • Vinh, Truong Quang;Kim, Young-Chul
    • ETRI Journal
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    • 제32권3호
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    • pp.380-389
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    • 2010
  • This paper presents a new edge-protection algorithm and its very large scale integration (VLSI) architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge-protection maps. Based on these maps, a two-step adaptive filter which includes offset filtering and edge-preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory-reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is verified on FPGA Cyclone II and implemented using the ANAM 0.25 ${\mu}m$ CMOS cell library. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details. The PSNR performance of our algorithm using pixel classification is better than that of previous algorithms using block classification.

Development Process of FPGA-based Departure from Nucleate Boiling Ratio Algorithm Using Systems Engineering Approach

  • Hwang, In Sok;Jung, Jae Cheon
    • 시스템엔지니어링학술지
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    • 제14권2호
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    • pp.41-48
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    • 2018
  • This paper describes the systems engineering development process for the Departure from Nucleate Boiling Ratio (DNBR) algorithm using FPGA. Current Core Protection Calculator System (CPCS) requirement and DNBR logic are analyzed in the reverse engineering phase and the new FPGA based DNBR algorithm is designed in the re-engineering phase. FPGA based DNBR algorithm is developed by VHSIC Hardware Description Language (VHDL) in the implementation phase and VHDL DNBR software is verified in the software Verification & Validation phase. Test cases are developed to perform the software module test for VHDL software modules. The APR 1400 simulator is used to collect the inputs data in 100%, 75%, and 50% reactor power condition. Test input signals are injected to the software modules following test case tables and output signals are compared with the expected test value. Minimum DNBR value from developed DNBR algorithm is validated by KEPCO E&C CPCS development facility. This paper summarizes the process to develop the FPGA-based DNBR calculation algorithm using systems engineering approach.

승강장 스크린 도어(PSD)에 대한 고 신뢰성의 감시 및 제어 시스템 개발 (Development of High Reliability Monitoring and Control System for Platform Screen Door)

  • 김진식;손진근
    • 전기학회논문지P
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    • 제59권2호
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    • pp.158-162
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    • 2010
  • PSD is automatically opened and closed when subway train arrive on the station. This system was designed to control electric automatic system. These doors will provide passenger safety, energy saving and a good environment in subway. The monitoring and control systems of PSD are configured so that they can be operated in automatic mode in connection with ATO through the composite control panel in the station control room. The objective of this paper is to obtain high reliability that is essential for monitoring and control systems of PSD. The power supply is based on protection circuit using DC power bridge from two UPS. Also, stable communication system consists of CAN communication line redundancy and RF cross protection algorithm. Monitoring state display results show the validity of the proposed high reliability monitoring and control systems of PSD.

Feedback Active Noise Control Based Voice Enhancing Ear-Protection System

  • Moon, Seong-Pil;Chang, Tae-Gyu
    • Journal of Electrical Engineering and Technology
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    • 제12권4호
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    • pp.1627-1633
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    • 2017
  • This paper proposes a voice enhancing ear-protection system which is based on feedback active noise control(FBANC). The proposed system selectively suppresses the background noise and preserves the talking voice by controlling the adaptive algorithm with the voice activity period detection module. The noise reduction performance of the proposed noise canceling algorithm is analytically derived for the two key performance affecting parameters, i.e., electro-acoustic coupling distance and noise bandwidth. The proposed system is also implemented with a floating-point DSP system and its performance is experimentally tested to compare with the analytically derived results. The achieved levels of noise reduction for the three different noise bandwidths cases, i.e., 10Hz, 50Hz, and 90Hz, are high to show 17.05dB, 10.54dB and 8.99dB, respectively. The feasibility of the proposed system is also shown by the peak noise reduction achieved more than 25dB while preserving the voice component in the frequency range between 200-800Hz.

분산전원 보호용 디지털 보호계전기 개발 (Development of the digital protection relay for protecting distributed generation)

  • 조철희;이병호;오의석;고철진;강상희
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2005년도 제36회 하계학술대회 논문집 A
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    • pp.181-183
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    • 2005
  • The existing distribution networks are growing with an increase of power demand more and more. Therefore, for efficient operation of distribution networks, operators are much in need of distributed generation. This paper describes a development of the digital protection relay(HIMAP) for protecting distributed generation which is expected to play an increasing role in electric power systems in the near future. This paper particularly introduces frequency protective algorithm and reverse power protective algorithm among the relaying algorithms for protecting distributed generation in distribution networks and resents capability of a developed digital protection relay including these algorithms.

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