• 대한전자공학회논문지
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• 제22권6호
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• pp.83-88
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• 1985

An electrically alterable read only memory with polysilicon gate is experimently realized employing a SONOS structure. The SONOS memory cells are proposed to achieve lower programming voltage with thin nitride (70A, 170$\AA$) layer. Its programming voltage is 10V (Tnit=70$\AA$), 22V(Tnit=170$\AA$). And the SONOS cell is able to, erasc biasing negative gate pulse, then its voltage is about -24V for nitride thickness of 170$\AA$.

• 전자공학회논문지D
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• 제34D권9호
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• pp.56-63
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• 1997

There generally exists a large variation in the thereshold voltages of the flash EEPROM cells after they are erased by using th fowler-nordheim tunneling, thereby getting some cells to be overeased. If the overerased cells are programmed with the conventional one-step programming scheme where an 12-13V pulse with the duration of 100.mu.S is applie don the control gate for the programming, they can suffer from the significant degradation of the reliability of the gate oxide. A two-step programming schem, where an 8/12 V pulse with a duration of 50.mu.S for each voltage is applied on the control gate for the programming, has been studied to solve the problem. The experimental results hav eshown that there is little difference in the programming characteristics between those two schemes, whereas the degradation of the gate oxide due to the programming can be significantly reduced with the two-step programming scheme compared to that with the one-step programming scheme. This is possibly because the positive charge stored in the floating gate of the overerased cells is compensate dwith the electrons injected into the floating gate while the 8V pulse is applied on the control gate, which leaves the overerased cells in the normally erased state after the duration of the 8V pulse.

• 대한전기학회논문지:전력기술부문A
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• 제55권11호
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• pp.447-452
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• 2006

This paper presents a scheme to solve the congestion problem with phase-shifting transformer(PST) controls and power generation controls using linear programming method. A good design of PST and power generation control can improve total transfer capability(TTC) in interconnected systems. This paper deals with an application of optimization technique for TTC calculation. Linear programming method is used to maximize power flow of tie line subject to security constraints such as voltage magnitude and real power flow in interconnected systems. The results are compared with that of repeat power flow(RPF) and sequential quadratic programming(SQP). The proposed method is applied to 10 machines 39 buses model systems to show its effectiveness.

• Advances in Energy Research
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• 제4권4호
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• pp.255-274
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• 2016

This paper presents a novel symbiotic organisms search (SOS) algorithm to optimize both real power loss (RPL) and voltage stability limit (VSL) of a transmission network by controlling the variables such as unified power flow controller (UPFC) location, UPFC series injected voltage magnitude and phase angle and transformer taps simultaneously. Mathematically, this issue can be formulated as nonlinear equality and inequality constrained multi objective, multi variable optimization problem with a fitness function integrating both RPL and VSL. The symbiotic organisms search (SOS) algorithm is a nature inspired optimization method based on the biological interactions between the organisms in ecosystem. The advantage of SOS algorithm is that it requires a few control parameters compared to other meta-heuristic algorithms. The proposed SOS algorithm is applied for solving optimum control variables for both single objective and multi-objective optimization problems and tested on New England 39 bus test system. In the single objective optimization problem only RPL minimization is considered. The simulation results of the proposed algorithm have been compared with the results of the algorithms like interior point successive linear programming (IPSLP) and bacteria foraging algorithm (BFA) reported in the literature. The comparison results confirm the efficacy and superiority of the proposed method in optimizing both single and multi objective problems.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1329-1330
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• 2007

Phase-change random access memory(PRAM) has many advantages compare with the existing memory. For example, fast programming speed, low programming voltage, high sensing margin, low power consume and long cyclability of read/write. Though it has many advantages, there are some points which must be improved. So, we invented and studied new constitution of $Ge_{1}Se_{1}Te_{2}$ chalcogenide material. Actually, the performance properties have been improved surprisingly. However, crystallization time was as long as ever for amorphization time. In this paper, we studied in order to make set operation time and reset operation voltage reduced. In the present work, by alloying Sb in $Ge_{1}Se_{1}Te_{2}$. we could confirm that improved its set operation time and reset operation voltage. As a result, the method of Sb-alloyed $Ge_{1}Se_{1}Te_{2}$ can be solution to decrease the set operation time and reset operation voltage.

• Journal of Electrical Engineering and Technology
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• 제4권3호
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• pp.330-336
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• 2009

This paper proposes an on-line voltage management and control solution for a distribution system which can improve the efficiency and accuracy of existing off-line work by collecting customer voltage on-line as well as the voltage compensation capability of the existing ULTC (Under Load Tap Changer) operation and control strategy by controlling the ULTC tap based on pattern clustering and recognition. The proposed solution consists of an ADVMD (Advanced Digital Voltage Management Device), a VMS (Voltage Management Solution) and an OLDUC (On-Line Digital ULTC Controller). An on-line voltage management emulator based on multi-thread programming and the shared memory method is developed to emulate on-line voltage management and digital ULTC control methodology based on the on-line collection of the customer's voltage. In addition, using this emulator, the effectiveness of the proposed pattern clustering and recognition based ULTC control strategy is proven for the worst voltage environments for three days.

• 한국전자통신학회논문지
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• 제9권3호
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• pp.279-284
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• 2014

본 논문에서는 p-채널 저온 다결정 실리콘 박막 트랜지스터의 문턱전압 변동을 보상할 수 있는 새로운 OLED 화소회로를 제안하였다. 제안한 5-TFT OLED 화소회로는 4개의 스위칭 박막 트랜지스터, 1개의 OLED 구동 박막 트랜지스터 및 1개의 정전용량으로 구성되어 있다. 제안한 화소회로의 한 프레임은 초기화 구간, 문턱전압 감지 및 데이터 기입 구간, 데이터 유지 구간 및 발광 구간으로 나누어진다. SmartSpice 시뮬레이션 결과, 구동 트랜지스터의 문턱전압이 ${\pm}0.25V$ 변동 시 최대 OLED 전류의 오차율은 -4.06%이였고 구동 트랜지스터의 문턱전압이 ${\pm}0.50V$ 변동 시 최대 OLED 전류의 오차율은 9.74%였다. 따라서 제안한 5T1C 화소회로는 p-채널 다결정 실리콘 박막 트랜지스터의 문턱전압 변동에 둔감하여 균일한 OLED 전류를 공급함을 확인하였다.

• 한국전자통신학회논문지
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• 제8권2호
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• pp.207-212
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• 2013

본 논문에서는 n-채널 저온 다결정 실리콘 박막 트랜지스터의 문턱전압 변동을 보상할 수 있는 전압 기입 AMOLED 화소회로를 제안하였다. 제안한 6T1C 화소회로는 5개의 스위칭 박막 트랜지스터, 1개의 OLED 구동 박막 트랜지스터 및 1개의 정전용량으로 구성되어 있다. SmartSpice 시뮬레이션 결과, 구동 트랜지스터의 문턱전압이 ${\pm}0.33$ V 변동시 최대 OLED 전류의 오차율은 7.05 %이고 Vdata = 5.75 V에서 OLED 양극 전압 오차율은 0.07 %로 제안한 6T1C 화소회로가 구동 트랜지스터의 문턱전압 변동에도 균일한 OLED 전류를 공급함을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.80-83
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• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by $0.35\;{\mu}m$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the two-bits per cell operation, charges must be locally trapped in the nitride layer above the channel near the junction. Channel hot electron (CHE) injection for programming can operate in multi-bit using localized trap in nitride film. CHE injection in our devices is achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The multi-bit operation which stores two-bit per cell is investigated with a reverse read scheme. Also, hot hole injection for fast erasing is used. Due to the ultra-thin gate dielectrics, our results show many advantages which are simpler process, better scalability and lower programming voltage compared to any other two-bit storage flash memory. This fabricated structure and programming characteristics are shown to be the most promising for the multi-bit flash memory.

• 대한전기학회논문지:전력기술부문A
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• 제52권10호
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• pp.584-592
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• 2003

This paper presents a fuzzy-GA method for the allocation and operation of dispersed generator systems(DGs) based on load model in composite distribution systems. Groups of each individual load model consist of residential, industrial, commercial, official and agricultural load. The problem formulation considers an objective to reduce power loss of distribution systems and the constraints such as the number or total capacity of DGs and the deviation of the bus voltage. The main idea of solving fuzzy goal programming is to transform the original objective function and constraints into the equivalent multi-objectives functions with fuzzy sets to evaluate their imprecise nature for the criterion of power loss minimization, the number or total capacity of DGs and the bus voltage deviation, and then solve the problem using genetic algorithm. The method proposed is applied to IEEE 12 bus and 33 bus test systems to demonstrate its effectiveness. .