• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1990년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 26-27 Oct. 1990
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• pp.634-638
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• 1990

In this paper, the architecture of a dataflow logic solving processor for programmable logic controller is proposed. As the proposed DFLSP (dataflow logic solving processor) is designed based on the dataflow architecture, it has inherently concurrent processing and data synchronization capabilities. The proposed DFLSP is adequate for high speed programmable logic controllers and gets rid of data synchronization problem in hardware level. The performance of the proposed DFLSP is analyzed using computer simulations and prototype hardware. With single processing element, the logic solving time is 144 usec per 1K steps of logic program and with eight processing elements, the logic solving time is 23 usec per 1K steps of logic program with reasonable assumptions.

• 융합신호처리학회논문지
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• 제20권3호
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• pp.118-124
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• 2019

최근 산업현장에서는 생산성, 품질, 고객 만족도를 향상시키기 위해 정보통신기술(ICT)을 기반으로 한 스마트 팩토리 체제로 전환하고 있다. 스마트 팩토리를 실현함에 있어 가장 중요한 장치는 무인 반송차(AGV)이며, AGV의 도입이 증가하고 있다. 일반적으로 AGV은 범용 PLC를 이용하여 개발하고 있으나, 범용 PLC로 개발된 AGV의 가격은 고가이며, 부피 또한 크다. 한편, 산업현장에서는 작업장의 공간적 제약 때문에 소형화, 용이한 재구성 등이 가능한 저가의 AGV를 요구하고 있다. 따라서 본 연구에서는 이러한 문제점을 해결하기 위해 PLC 내장형 AGV 제어기의 설계법을 제안하고, 그 성능을 평가하였다. 그 결과, 우수한 속도제어와 주행 정밀도(속도제어 오차=0.021[m/s], 주행자세제어의 평균오차 = 2.1[mm])를 보였다. 이와 같이 제안된 AGV 제어기를 산업현장에 적용한다면, 저비용으로 소형화와 재구성 등이 가능할 것이다.

• 대한전기학회논문지
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• 제40권8호
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• pp.836-844
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• 1991

PLC(programmable logic controller) system is widely used for the control of factory. PLC system receives ladder diagram which is drawn by the user to implement hardware logic, converts the ladder diagram into sequence program which is executable in the PLC system, and executes the sequence program indefinitely unless user breaks. The sequence program processes the data of on/off signal, and endures 1 scan delay and missing of pulse-type signal shorter than a scan time. So, data dependency doesn't exist. By applying theis characteristics to multiprocessor architecture, we design parellel PLC functionally and evaluate performance upgrade. Parallel PLC consists of central processing module, N general processing unit, and a shared memory by master-slave type. Each module executes allocated sequence program by the control of central processing module. We can expect performance upgrade by parallel processing, and reliability by relocation of sequence program when error occurs in processing module.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.735-738
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• 1998

To develop an effective virtual prototyping methodology for the PLC(Programmable Logic Controller) based real-time systems, a conversion algorithm from RLL(Relay Ladder Logic) to statechart is presented in this paper. The RLL is the main programming language to represent the operation of the PLC, and the statechart is the most widely used tool in the field of virtual prototyping in order to represent the behaviour of real-time systems. A virtual prototyping for an example case is implemened to evaluate the benefit of the proposed algorithm.

• 동력기계공학회지
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• 제8권1호
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• pp.62-68
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• 2004

This paper describes a fault tolerant control in distributed PLC(Programmable Logic Controller) system to ensure reliability of controllers which have some faults simultaneously. First, the behavior of PLC is modeled as discrete expressions using Galois field. Then, we design the control laws for additional spare controllers to generate parity code with two dimensions. Finally, the algorithm for estimating normal output instead of abnormal output from the controllers with fault is suggested. Comparing to the traditional duplication method, the suggested method can reduce the number of spare controllers significantly to ensure control reliability. This method will be applied to an automatic system in order to increase reliability. Also, it can improve cost performance of the system.

• 한국농업기계학회:학술대회논문집
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• 한국농업기계학회 1998년도 동계 학술대회 논문집
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• pp.174-179
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• 1998

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.1386-1389
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• 1993

We are describing the architecture of a fuzzy logic controller using pulse-width-modulation (PDM) technique and a pipeline structure. Features of this controller are: A new architecture for the inference unit, reduced chip area and less I/O-pins. Additionally we present two different rule-bases: one hardwired with reduced chip-area and the other programmable for prototyping. Also an architecture of a parallel minimum-gate is shown.

• 제어로봇시스템학회논문지
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• 제20권7호
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• pp.741-749
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• 2014

This paper proposes a machine vision module for PLCs (Programmable Logic Controllers). PLC is the industrial controller most widely used in factory automation system. However most of the machine vision systems are based on PC (Personal Computer). The machine vision system embedded in PLC is required to reduce the cost and improve the convenience of implementation. In this paper, we newly propose a machine vision module based on PLC. The image processing libraries are implemented and integrated with the PLC programming tool. In order to interface the libraries with ladder programming, the ladder instruction set was also designed for each vision library. By use of the developed system, PLC users can implement vision systems easily by ladder programming. The developed system was applied to sample inspection system to verify the performance. The experimental results show that the proposed system can reduce the cost of installing as well as increase the ease-of-implementation.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1016-1021
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• 2003

The overall size of electronic product is becoming small according to development of technology. Accordingly it is difficult to inspect these small components by human eyes. So, an automation system for inspecting them has been used. The existing system put microprocessor or Programmable Logic Controller (PLC) use. The structure of microprocessor-based controller and PLC use basically composed of memory devices such as ROM, RAM and I/O ports. Accordingly, the system is not only becomes complicated and enlarged but also higher price. In this paper, we implement FPGA-based One-chip Programmable Timing Controller for Inspecting Small components to resolve above problems and design the high performance controller by using VHDL. With fast development, the FPGA of high capacity that can have memory and PLL have been introduced. By using the high-capacity FPGA, the peripherals of the existent controller, such as memory, I/O ports can be implemented in one FPGA. By doing this, because the complicated system can be simplified, the noise and power dissipation problems can be minimized and it can have the advantage in price. Since the proposed controller is organized to have internal register, counter, and software routines for generating timing signals, users do not have to problem the details about timing signals and need to only send some values about an inspection system through an RS232C port. By selecting theses values appropriate for a given inspection system, desired timing signals can be generated.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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• pp.279-283
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• 1987

In this paper an intelligent supervisory programmable controller for automatic assembly machine is developed. This is achieved by adding sequence control hardware with input-interrupts to supervisory real time language and also by incorporating an automatic planning method which uses a predicate logic model and an action model. The designed intelligent supervisory programmable controller is applied to Die Bonding Machine and is to found to work well.