• Title/Summary/Keyword: Programmable Filter

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Improved Programmable-Dynamometer Control For Traction Drive System Testing (견인구동시스템 시험을 위한 개선된 프로그램어블 다이나모메터 제어)

  • Kim G.D;Hong J.S;Shin J.R;Lee W.D;Han S.Y
    • Proceedings of the KSR Conference
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    • 2003.05a
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    • pp.427-432
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    • 2003
  • The control method of programmable dynamometer for overall test of machine is to load the reference torque which is computed from torque transducer into motor under test. But the torque information detected from torque transducer have a lot of noise when the load torque of moter is a small quantity or changing. Thus, torque transducer must have a low pass filter to detect a definite torque information. But The torque delay generated by filter with torque transducer occur a torque trouble for meter torque of programmable dynamometer. The proposed system improved the problem of the torque measuring delay with torque transducer, and the load torque is estimated by the minimal order state observer based on the torque component of the vector control induction meter. Therefore, the torque controller is not affected by a load torque disturbance.

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Programmable-Dynamometer Control For Traction Motor Testing (전동기 시험을 위한 프로그램어블 다이나오메터 제어)

  • Kim, G.D.;Hong, J.S.;Ahn, T.K.;Lee, H.Y.;Shin, J.R.;Han, S.Y.
    • Proceedings of the KIEE Conference
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    • 2003.07b
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    • pp.1108-1110
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    • 2003
  • The control method of programmable dynamometer for overall test of machine is to load the reference torque which is computed from torque transducer into motor under test. But the torque information detected from torque transducer have a lot of noise when the load torque of meter is a small quantity or changing. Thus, torque transducer must have a low pass filter to detect a definite torque information. But The torque delay generated by filter with torque transducer occur a torque trouble for meter torque of programmable dynamometer. The proposed system improved the problem of the torque measuring delay with torque transducer, and the load torque is estimated by the minimal order state observer based on the torque component of the vector control induction moter. Therefore, the torque controller is not affected by a load torque disturbance.

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Sensorless Vector Control for Non-salient Permanent Magnet Synchronous Motors using Programmable Low Pass Filter (프로그래머블 저역통과 필터를 이용한 비돌극형 영구자석 동기전동기 센서리스 벡터제어)

  • Yu, Jae-Sung;Lee, Dong-Yup;Won, Chung-Yuen;Lee, Byoung-Kuk
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.20 no.10
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    • pp.74-81
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    • 2006
  • This paper proposes the sensorless vector control scheme of a Non-salient permanent-magnet synchronous motor (SPMSM) using programmable low pass filter (PLPF) to estimate a stator flux with the information of a rotor position and speed. The sesorless vector control of PMSM using PLPF can solves the dc drift problem associated with a pure integrator and a LPF. Also, the PLPF has the phase and gain compensator to estimate exactly rotor position and speed. Therefore, the information of a position and speed is exactly estimated because the drift and offset problems are solved by the PLPF. The experimental results show good performance over the 10[%] of the rated speed and under load condition.

Speed Sensorless Vector Control of Induction Motors with an Improved Stator Flux Estimator (개선된 고정자 자속 추정을 통한 유도전동기의 속도센서리스 벡터제어)

  • 신명호;현동석;조순봉;최종률
    • Proceedings of the KIPE Conference
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    • 1998.07a
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    • pp.371-375
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    • 1998
  • This paper proposes a programmable low pass filter(LPF) to estimate stator flux for speed sensorless stator flux orientation control of induction motors. The programmable LPF is developed to solve the dc drift problem associated with a pure integrator and an analog LPF with fixed pole. of the programmable LPF is located far from the origin in order to decrease the time constant as speed increases. The programmable LPF has the phase and the magnitude compensator to exactly estimate stator flux in a wide speed range. So, the drift problem is much improved and the stator flux is exactly estimated in the wide speed range. The validity of the proposed programmable LPF is verified by speed sensorless vector control of a 2.2[kW] three-phase induction motor.

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A High-Speed Matched Filter for Searching Synchronization in DSSS Receiver (DSSS 수신기에서 동기탐색을 위한 고속 정합필터)

  • 송명렬
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.10C
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    • pp.999-1007
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    • 2002
  • In this paper, the operation of matched filter for searching initial synchronization in direct sequence spread spectrum receiver is studied. The implementation model of the matched filter by HDL (Hardware Description Language) is proposed. The model has an architecture based on parallelism and pipeline for fast processing, which includes circular buffer, multiplier, adder, and code look-up table. The performance of the model is analyzed and compared with the implementation by a conventional digital signal processor. It is implemented on a FPGA (Field Programmable Gate Array) and its operation is validated in a timing simulation result.

SPEED SENSORLESS FIELD-ORINTED CONTROL OF INDUCTION MOTORS WITH AN IMPROVED FLUX ESTMATOR

  • Shin, Myoung-Ho;Hyun, Dong-Seok;Cho, Soon-Bong;Choe, Song-Yul
    • Proceedings of the KIPE Conference
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    • 1998.10a
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    • pp.392-397
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    • 1998
  • This paper proposes a programmable low pass filter(LPF) to estimate stator flux for speed sensorless stator flux orientation control of induction motors. The programmable LPF is developed to solve the dc drift problem associated with a pure integrator and a LPF with fixed pole. The pole of the programmable LPF is located far from the origin to decrease the time constant as speed increases. The programmable LPF has the phase and the magnitude compensator to exactly estimate stator flux in a wide speed range. So, the drift problem is much improved and the stator flux is exactly estimated in the wide speed range.

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An Efficient FPGA based Real-Time Implementation Shunt Active Power Filter for Current Harmonic Elimination and Reactive Power Compensation

  • Charles, S.;Vivekanandan, C.
    • Journal of Electrical Engineering and Technology
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    • v.10 no.4
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    • pp.1655-1666
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    • 2015
  • This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

SoC Implementation of Deblocking Filter for Block-based Compressed Images and Videos (블록 기반 압축 이미지 및 비디오를 위한 디블로킹 필터의 SoC 구현)

  • Seo, Gwang-Seok;Lee, Joo-Heung
    • Journal of IKEEE
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    • v.23 no.3
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    • pp.925-933
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    • 2019
  • In this paper, we implement ZYNQ SoC-based post-processing system that utilizes partial reconfiguration to remove blocking artifacts generated by compression algorithm. Hardware implementation of the deblocking filter in a Field Programmable Gate Array (FPGA) provides high computational capability and can be partially reconfigured to process 1080p images in real time. Partially reconfigurable areas in FPGA can be utilized to use hardware more efficiently in highly resource-constrained embedded systems. Experimental results of the proposed system show improvement of visual quality both objectively and subjectively with 0.6dB higher PSNR after deblocking filtering process. The measured power consumption of the deblocking filter during run-time is 68.33mW.

Design of Programmable SC Filter (프로그램 가능한 SC Filter의 설계)

  • 이병수;이종악
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.11 no.3
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    • pp.172-178
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    • 1986
  • The recent interest in the design of filters is motivatied by the fact that such filter can be fully integrated using standard metal-oxide-semiconductor processing technology. This is due to replacing all the resistors in the active RC filter network by the switched capacitors. The voltage gain of a SC filter depends only on the rations of capacitance and these ratios can be obtained and maintained to high accuracy. Therefore, it is known that a switched capacitor is much better than a resistor in temperature and linearity characteristics. This paper proposed a programmable SC filter and proved the fact that ${omega}_0$ Q and G of this circuit can be controlled by digital signal. Experiments show that SC filter remains the low sensitivities but it can't avoid little influence of parasitic capacitance. As the transfer characteristic of the SC filter is varied with sampling frequency and resistor array, SC filtering technigue can be applied for digital processing, speech analysis and synthesis and so on.

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