• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.3
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• pp.249-255
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• 2017

The finger vein recognition technology is a method to acquire a finger vein image by illuminating infrared light to the finger and to authenticate a person through processes such as feature extraction and matching. In order to recognize a finger vein, a 2D mask-based two-dimensional convolution method can be used to detect a finger edge but it takes too much computation time when it is applied to a low cost micro-processor or micro-controller. To solve this problem and improve the recognition rate, this study proposed an extraction method for the region of interest based on virtual core points and moving average filtering based on the threshold and absolute value of difference between pixels without using 2D convolution and 2D masks. To evaluate the performance of the proposed method, 600 finger vein images were used to compare the edge extraction speed and accuracy of ROI extraction between the proposed method and existing methods. The comparison result showed that a processing speed of the proposed method was at least twice faster than those of the existing methods and the accuracy of ROI extraction was 6% higher than those of the existing methods. From the results, the proposed method is expected to have high processing speed and high recognition rate when it is applied to inexpensive microprocessors.

• The Journal of Korean Institute of Next Generation Computing
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• v.15 no.2
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• pp.39-49
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• 2019

Recently, CPU-GPU integrated heterogeneous multicore processors have been widely used for improving the performance of computing systems. Heterogeneous multicore processors integrate CPUs and GPUs on a single chip where CPUs and GPUs share the LLC(Last Level Cache). This causes a serious cache contention problem inside the processor, resulting in significant performance degradation. In this paper, we propose the partitioned LLC architecture to solve the cache contention problem in heterogeneous multicore processors. We analyze the performance impact varying the LLC size of CPUs and GPUs, respectively. According to our simulation results, the bigger the LLC size of the CPU, the CPU performance improves by up to 21%. However, the GPU shows negligible performance difference when the assigned LLC size increases. In other words, the GPU is less likely to lose the performance when the LLC size decreases. Because the performance degradation due to the LLC size reduction in GPU is much smaller than the performance improvement due to the increase of the LLC size of the CPU, the overall performance of heterogeneous multicore processors is expected to be improved by applying partitioned LLC to CPUs and GPUs. In addition, if we develop a memory management technique that can maximize the performance of each core in the future, we can greatly improve the performance of heterogeneous multicore processors.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• Journal of the Korea Society of Computer and Information
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• v.17 no.8
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• pp.11-19
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• 2012

In this paper, we propose a power-efficient scheduling scheme for lightly loaded multicore processors which contain more processing cores than running tasks. The proposed scheme activates a portion of available cores and inactivates the other unused cores in order to save power consumption. The tasks are assigned to the activated cores based on a heuristic mechanism for fast task assignment. Each activated core executes its assigned tasks with the optimal clock frequency which minimizes the power consumption of the tasks while meeting their deadlines. Evaluation shows that the proposed scheme saves up to 78% power consumption of the previous method which activates as many processing cores as possible for the execution of the given tasks.

• Journal of Digital Convergence
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• v.13 no.8
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• pp.245-251
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• 2015

If a digital signage system is operated in PC mounted in the Window OS then the implementing price is very high. For resolving this problem, we used the Smartphone mounted in ARM Cortex family of multi-core processor-based mobile platform. We developed a low-power low-cost digital signage system and a remote convergence content management program based on web server. This convergence system manages advertising content to a remote control device anywhere using remote control technology. This system is one integrated system with display and is a low-power consumed and is developed in very efficient hardware interface. And condition sensors(intensity of illumination, temperature, weather, GPS etc) is equipped in the developed system. Automatic contents builder and Context-aware SMIL module is also implemented in the convergence system. We achieved over 50% power savings comparing with conventional Window OS system and 16 points multi-touch in our system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.53-58
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• 2006

A Vertex Shader is designed to show more 3D graphics expressions, and to increase flexibility of the fixed function T&L (Transform and Lighting) engine. Design of this Shader is based on Vertex Shader 1.1 of DirectX 8.1 and OpenGL ARB. The Vertex Shader consists of four floating point ALUs for vectors operation. The previous 32bits floating point data type is replaced to 24bits floating point data type in order to design the Vertex Shader that consume low-power and occupy small area. A Xilinx Virtex2 300M gate module is used to verify behaviour of the core. The result of Synopsys synthesis shows that the proposed Vertex Shader performs 115MHz speed at the TSMC 0.13um process and it can operate as the rate of 12.5M Polygons/sec. It shows the complexity of 110,000 gates in the same process.

• Journal of IKEEE
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• v.15 no.1
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• pp.104-112
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• 2011

During the ground operation of Korean army, the voice message is mainly used for exchanging informations related to the surveillance and reconnaissance, command and control, and precision strike. However, in order to the battlefield visualization among fighting powers participating in the ground force operation, automatic situational awareness and variable message format (VMF) for command and control are required. For securing core technologies necessary for the battlefield visualization, message standard and message handler are established through several applied researches. Besides, the VMF for equipping a weapon system is in development. In this paper, a study on the Korean variable message format (KVMF), where interoperability of integrated battle management system (BMS) is guaranteed due to performing joint, ground, and combined operations so that the situation awareness and strike system can be automated in almost real time, is presented. From the modeling and simulation (M&S) results of the message processor, delay time is varied in accordance with the number of nodes in unit platoon network, message length, and generation interval of routine messages. Therefore, it is shown that the system performance can be optimized by establishing proper network protocol for each situation.

• Journal of Broadcast Engineering
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• v.16 no.6
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• pp.941-950
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• 2011

With the recent advance in the performance of mobile phones, many effective interfaces for them have been proposed. This paper implements a hand-gesture-and-vision-based interface on a mobile phone. This paper assumes natural interaction scenario when user holds a mobile phone in a hand and sees the other hand's palm through mobile phone's camera. Then, a virtual object is rendered on his/her palm and reacts to hand and finger movements. Since the implemented interface is based on hand familiar to humans and does not require any additional sensors or markers, user freely interacts with the virtual object anytime and anywhere without any training. The implemented interface worked at 5 fps on mobile phone (Galaxy S2 having a dual-core processor).

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.844-847
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• 2005

A seamless analysis of complex geometry is one of greatly interesting topic. However, there are still gaps between the industrial applications and fundamental academic studies owing to time consuming modeling process. To resolve this problem, an auto mesh generation program based on grid-based approach has been developed for IT-product in the present study. At first, base mesh and skin mesh are generated using the information of entities which extracted from IGES file. Secondly the provisional core mesh with rugged boundary geometry is constructed by superimposing the skin mesh as well as the base mesh generated from the CAD model. Finally, the positions of boundary nodes are adjusted to make a qualified mesh by adapting node modification and smoothing techniques. Also, for the sake of verification of mesh quality, the hexahedral auto mesh constructed by the program is compared with the corresponding tetrahedral free mesh and hexahedral mapped mesh through static finite element analyses. Thereby, it is anticipated that the grid-based approach can be used as a promising pre-processor for integrity evaluation of various IT-products.

• Journal of KIISE:Databases
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• v.37 no.5
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• pp.275-284
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• 2010

GPUs are stream processors based on multi-cores, which can process large data with a high speed and a large memory bandwidth. Furthermore, GPUs are less expensive than multi-core CPUs. Recently, usage of GPUs in general purpose computing has been wide spread. The CUDA architecture from Nvidia is one of efforts to help developers use GPUs in their application domains. In this paper, we propose techniques to parallelize a skyline algorithm which uses a simple nested loop structure. In order to employ the CUDA programming model, we apply our optimization techniques to make our skyline algorithm fit into the performance restrictions of the CUDA architecture. According to our experimental results, we improve the original skyline algorithm by 80% with our optimization techniques.