• 한국산학기술학회논문지
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• 제1권2호
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• pp.27-31
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• 2000

대상 물체의 온도분포를 해석하고 계측하기 위해 열상 장비가 구현된다. 시스템의 주요한 부분은 초점면 배열 형태의 센서가 적용된 열상 카메라이다. 적용된 열상 센서는 중파장 적외선 영역의 신호를 검출하며 열상을 형성하기 위한 기본 신호를 출력한다. DSP가 활용되어 센서 신호처리를 통해 열상을 구성하고 NTSC 신호 및 디지털 신호 출력을 한다. 열상의 화질을 개선하기 위해 이점 교정법을 적용한다. 이는 낮은 온도와 높은 온도를 기준으로 하여 초점면 배열 센서 화소 신호의 공간적인 비균일함을 교정하는 것으로서 실험 결과를 통해 열상의 화질이 개선됨을 보인다.

• 한국통신학회논문지
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• 제18권7호
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• pp.970-979
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• 1993

본 논문에서는 이진영상처리를 위한 다기능 프로세서를 구현하였다. 프로세서는 주소 발생부, 윈도우 파이프 라인, 룩-업 테이블, 제어부, 2개의 메모리부로 구성하였다. 본 프로세서는 기존의 SAP(Serial Array Processor)설계 기법과 비교하여 구조가 단순하며 처리속도가 향상되었다. 또한 간단한 소프트웨어 선택에 의해서 영상크기를 선정하며 윤곽검출, 특징점 추출, 세선화, 평활화등의 기능을 선택적 또는 순차적으로 수행 가능하도록 하였다.

• 전자공학회논문지S
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• 제35S권1호
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• pp.105-113
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• 1998

A new image processor is implemented for high-speed digital copiers and facsimiles. The imgage processor performs CCD and CIS interface, pre-processing, enlargement andreduction of gray level image, and various halftoning algorithms. Implemented halftoning algorithms are simple thresholding, fuzzy based mixed mode thresholding, dithering, and edge enhanced error diffusion. The result of binarization is transferred to a printer with serial or paralel output ports. Line by line pipelined data prodessing architecture is employed with time sharing access of the external memory. In receiving mode, it converts the resolution of received binary image for compatibility with conventional facsimile. In copy mode, a line of A3 paper with 400 dpi is processed with in 2.5 ms. The prototype of image processor was implemented usig Laser Programmable Gate Array (LPGA) with 0.8.mu.m technology.

• 전자공학회논문지C
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• 제34C권8호
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• pp.71-78
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• 1997

An LPC cepstrum processor for speech recognition is implemented on CMOS array process. The designed processor contains a 24-bit floating-point MAC unit to perform the correlation quickly, which occupies the majority of operations used in the algorithm, and has 22 register files to store temporary variables. For the purpose of fast operations, the floating-point MAC consists of a 3-stage pipeline and the new post-normalization shceme is proposed and applied to it. Experimental result shows that it takes approximately 266.mu.s to process 200 samples/frame at 15 MHz clock rate. This processor runs at the maximum rate of 16.6 MHz and the number of gates are 27,760.

• 대한전자공학회논문지
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• 제27권7호
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• pp.1005-1014
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• 1990

This paper proposes the control unit of a 32-bit high-performance RISC type microprocessor. This control unit controls the whole data path of target processor and on chip instruction/data caches in 4-stage pipelined scheme. For the improvement of speed, large parts of data path and control unit are designed by domino-CMOS and hard-wired circuit technology. First, in this paper, target processor's instruction set and data path are defined, and next, all signals needed to control the data path are analyzed. The decoder of control unit and clock generated logic block are implemented in DCAL(Dynamic CMOS Array Logic) with modified clock scheme for the purpose of speed up and supporting RISC processor's pipelined architecture efficiently.

• IEIE Transactions on Smart Processing and Computing
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• 제4권2호
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• pp.83-88
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• 2015

Core-A is 32-bit synthesizable processor core with a unique instruction set architecture (ISA). In this paper, the Core-A ISA is introduced with discussion of useful features and the development environment, including the software tool chain and hardware on-chip debugger. Core-A is described using Verilog-HDL and can be customized for a given application and synthesized for an application-specific integrated circuit or field-programmable gate array target. Also, the GNU Compiler Collection has been ported to support Core-A, and various predesigned platforms are well equipped with the established design flow to speed up the hardware/software co-design for a Core-A-based system.

• Journal of the Optical Society of Korea
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• 제9권3호
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• pp.111-118
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• 2005

In this paper, a new optical parallel binary arithmetic processor (OPBAP) capable of computing arbitrary n-bit look-ahead carry full-addition is proposed and implemented. The conventional Boolean algebra is considered to implement OPBAP by using two schemes of optical logic processor. One is space-variant optical logic gate processor (SVOLGP), the other is shadow-casting optical logic array processor (SCOLAP). SVOLGP can process logical AND and OR operations different in space simultaneously by using free-space interconnection logic filters, while SCOLAP can perform any possible 16 Boolean logic function by using spatial instruction-control filter. A dual-rail encoding method is adopted because the complement of an input is needed in arithmetic process. Experiment on OPBAP for an 8-bit look-ahead carry full addition is performed. The experimental results have shown that the proposed OPBAP has a capability of optical look-ahead carry full-addition with high computing speed regardless of the data length.

• 한국전자파학회논문지
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• 제16권7호
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• pp.740-745
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• 2005

본 논문은 GSM 시스템의 다경로 환경에서 선형 제약형 어레이 처리기를 이용하여 주종형 어레이 처리와 공간 유화 방법으로 원하는 신호를 추정하는 성능에 대하여 논한다. SINR과 BER 성능에서 주종형 어레이 처리방법과 공간유화 방법이 선형 제약형 어레이 처리방법보다 우수한 반면, 공간 유화 방법의 성능이 주종형 어레이 처리기 보다 더 나은 것으로 나타났다.

• 대한전자공학회논문지
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• 제26권8호
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• pp.1178-1186
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• 1989

In this paper, a systolic array for polyadic-nonserial DP problems is designed, the performance is analyzed and the efficient operating method is proposed. The algorithm is transformed to remove the broadcasting and global communication paths in the data dependence step by step. The transformed algorithm is mapping to the systolic array using the method proposed by D. I. Moldovan. The designed array is homogenous, had the processing elements of (n+1)/2 and 2n computation time ( n is the size of problem). In case of being many problems to process, the efficiency of array can be upward by inputing the problems successively. The interval between the initiations of two successive proboem instances is [n/2]+1 and the speed-up is about 4. The processor utilizations of each case are calculated.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 1999년도 추계종합학술대회
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• pp.173-176
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• 1999

최근 화상 회의 시스템에서 화자 위치 추정 및 음질 향상 기술이 연구되고 있다. 이 시스템에서는 마이크로폰 어레이를 이용, 화자의 위치를 파악하여 화자의 방향으로 카메라를 자동으로 조정해 주게 된다. 본 연구에서는 마이크로폰 어레이를 통해 수신된 신호를 이용하여 Matched Filter Array를 구성하고 음질을 향상시켰다. 이때 역변환 필터로써 IIR필터를 사용하여 계산량을 줄였으며, 범용DSP 프로세서를 이용한 하드웨어를 제작하여 그 성능을 확인하였다.