• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.368-371
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• 1999

In this paper, we propose a neural network processor architecture with on-chip learning and with reconfigurability according to the data dependencies of the algorithm applied. For the neural network model applied, the proposed architecture can be configured into either SIMD or SRA(Systolic Ring Array) without my changing of on-chip configuration so as to obtain a high throughput. However, changing of system configuration can be controlled by user program. To process activation function, which needs amount of cycles to get its value, we design it by using PWL(Piece-Wise Linear) function approximation method. This unit has only single latency and the processing ability of non-linear function such as sigmoid gaussian function etc. And we verified the processing mechanism with EBP(Error Back-Propagation) model.

• 한국음향학회:학술대회논문집
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• 한국음향학회 1991년도 학술발표회 논문집
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• pp.163-168
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• 1991

In this paper, we propose a new systolic architecture for the order statistics(OS) constant false alarm rate(CFAR) processor. In the proposed architecture, each processing element(PE) can compare two reference data cells with one test cell simultaneously in each clock cycle. So the utilization of each PE in this architecture is 100% whereas the utilization of each PE in the systolic architecture previously reported by Ritcey and Hwang is 50% because of one clock delay between two adjacent PE's active in computation. This can speed up the data processing rate by a factor of two. With this architecture, we can obtain the reduced number of communication links between adjacent PE's and reduction of the latency by half in comparison with the one proposed by Ritcey and Hwang.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 1999년도 추계종합학술대회
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• pp.169-172
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• 1999

수중 음원을 탐지할 때 사용되는 정합장 처리 기법은 복잡한 수중 환경을 고려하여 수행된다. 특히, 최소 분산 처리기를 적용할 경우 행렬의 고유치 문제로 인해 그 성능이 크게 저하될 수 있다. 본 논문에서는 변환 행렬을 이용하여 최소 분산 정합장 처리기의 성능을 개선하였다 이 변환 행렬은 입력 신호의 공분산 행렬이 역행렬을 구할 수 있도록 하면서 원하는 음원 신호 성분을 향상시키도록 한다. 제안된 방법은 NATO 산하 SACLANT 센터에서 수집된 실측 데이터를 이용하여 그 효율성을 입증하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 B
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• pp.1368-1370
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• 2005

Satellite is operated only with internal battery when separated from rocket. Internal battery is charged only from SAR(solar Array Regulator), solar cell. So battery will be exhausted and purpose of satellite will be failed if load module is out of order or short. This paper proposed real time current limiter which operated by telemetry of outer processor. This current limiter operates by control signal simultaneously cuts off over current by self over current sensing circuit. So it can reduce waste of battery energy and over load of outer processor.

• 대한전자공학회논문지
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• 제23권3호
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• pp.345-350
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• 1986

This paper deseribes the design of a vector-coordinate rotation processor and the apporoximate evaluations of sine and consine based upon the use of residue number systems. The proposed algorithm results in a considerable improvement of computational speed as compared to the CORDIC algorithm. According to the results of computer simulation, the mean error of sine and cosine is 0.0025, and the mean error of coorcinate rotation arithmatic is 0.65. The proposed processor has the efficiency for the design and fabrication of integrated circuits, because it consists of an array of identical lookup tables.

• Journal of Power Electronics
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• 제12권1호
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• pp.164-171
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• 2012

Variable step size maximum power point trackers (MPPTs) are widely used in photovoltaic (PV) systems to extract the peak array power which depends on solar irradiation and array temperature. One essential factor which judges system dynamics and steady state performances is the scaling factor (N), which is used to update the controlling equation in the tracking algorithm to determine a new duty cycle. This paper proposes a novel stability study of variable step size incremental resistance maximum power point tracking (INR MPPT). The main contribution of this analysis appears when developing the overall small signal model of the PV system. Therefore, by using linear control theory, the boundary value of the scaling factor can be determined. The theoretical analysis and the design principle of the proposed stability analysis have been validated using MATLAB simulations, and experimentally using a fixed point digital signal processor (TMS320F2808).

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1157-1160
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• 1998

This paper describes the design of a block data flow architecture(BDFA) which implements 2-D discrete wavelet transform(DWT)/inverse discrete wavelet transform(IDWT) for real time image processing applications. The BDFA uses 2-D product separable filters for DWT/IDWT. It consists of an input module, a processor array, and an output module. It use both data partitioning and algorithm partitioning to achieve high efficiency and high throughput. The 2-D DWT/IDWT algorithm for 256$\times$256 lenna image has been simulated using IDL(Interactive Data Language). The 2-D array structured BDFA for the 2-D filter has been modeled and simulated using VHDL.

• 대한의용생체공학회:학술대회논문집
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• 대한의용생체공학회 1995년도 추계학술대회
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• pp.278-281
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• 1995

In this paper, we have developed EEG (electroencephalography) analyzer for monitoring the condition of brain in neurological surgery. This system is composed of EEG amplifier. personal-computer and BSP (Digital Signal Processor). By parallel processing of DSP, this system can analysis the power spectral density change of EEG in real-time and display the CSA(Compressed Spectral Array) and CDSA(Color Density Spectral array) of EEG. This system was tested by real EEG and showed the change of EEG.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 추계학술대회 논문집
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• pp.5-6
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• 2012

In this paper, a simplified maximum power point tracking technique for the solar charger is presented. Main advantages of the proposed charger include low cost and optimized charge time. The maximum power point tracking method is used to deliver the maximum power from PV array to the battery thereby reducing the charge time. Moreover, the proposed technique which tracks the maximum power point by adjusting output current helps reduce the quantity of required number of sensors for the charger. The experimental protype was implemented by using an 80W PV array, a buck converter and a digital signal processor to verify the feasibility of the proposed method.

• Journal of information and communication convergence engineering
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• 제8권5호
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• pp.570-574
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• 2010

A thinning algorithm changes a binary fingerprint image to one pixel width. A thinning stage occupies 40% cycle of 32-bit RISC microprocessor system for a fingerprint identification algorithm. Hardware block processing is more effective than software one in speed, because a thinning algorithm is iteration of simple instructions. This paper describes an effective hardware scheme for thinning stage processing using the Verilog-HDL in $160\times192$ Pixel Array. The ZS algorithm was applied for a thinning stage. The hardware scheme was designed and simulated in RTL. The logic was also synthesized by XST in FPGA environment. Experimental results show the performance of the proposed scheme.