• 정보학연구
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• 제10권3호
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• pp.33-45
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• 2007

Systolic Array Processor is used for designing the special purpose processor in Digital Signal Processing, Computer Graphics, Neural Network Applications etc., since it has the characteristic of parallelism, pipeline processing and architecture of regularity. But, in case of using general design method, it has intial waiting period as large as No. of PE-1. And if the connected system needs parallel and simultaneous outputs, processor has some problems of the performance, since it generates only one output at each clock in output state. So in this paper, one dimensional Systolic Array Processor that is designed according to the dependance of data and operations using the partitioned sub-matrix is proposed for the purpose of improving the performance. 1-D Systolic Array using 4 partitioned sub-matrix has efficient method in case of considering those two problems.

• 전자공학회논문지B
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• 제30B권2호
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• pp.44-50
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• 1993

In this paper, we will present an array processor for implementation of digital neural networks. Back-propagation model can be formulated as a consecutive matrix-vector multiplication problem with some prespecified thresholding operation. This operation procedure is suited for the design of an array processor, because it can be recursively and repeatedly executed. Systolic array circuit architecture with Residue Number System is suggested to realize the efficient arithmetic circuit for matrix-vector multiplication and compute sigmoid function. The proposed design method would expect to adopt for the application field of neural networks, because it can be realized to currently developed VLSI technology.

• 전자공학회논문지B
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• 제30B권7호
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• pp.1-13
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• 1993

In this paper, the problems of the conventional special-purpose array processor such as the deficiency of flexibility have been investigated. Then, a new modified methodology has been suggested and applied to obtain the common solution of the three typical App algorithms like SP(Shortest Path), TC(Transitive Closure), and MST(Minimun Spanning Tree) among the various APP algorithms using the similar method to obtain the solution. In the newly proposed APP parallel algorithm, real-time Processing is possible, without the structure enhancement and the functional restriction. In addition, we design 2-demensional bit-parallel low-triangular systolic array processor and the 1-PE in detail. For its evaluation, we consider its computational complexity according to bit-processing method and describe relationship of total chip size and execution time. Therefore, the proposed processor obtains, on which a large data inputs in real-time, 3n-4 execution time which is optimal o(n) time complexity, o(n$^{2}$) space complexity which is the number of total gate and pipeline period rate is one.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1488-1491
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• 1987

This paper describes 16-point FFT processor using systolic array and its implementation into VLSI. Designed FFT processor executes FFT/IFFT arithmetic under mode control and consists of cell array, array controller and input/output buffer memory. For design for testibility, we added built-in self test circuit into designed FFT processor. To verify designed 16-point FFT processor, logic simulation was performed by YSLOG on MICRO-VAXII. From the simulation results, it is estimated that the proposed FFT processor can perform 16-point FFT in about 4400[ns].

• 한국정보처리학회논문지
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• 제5권8호
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• pp.1972-1984
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• 1998

• 전자공학회논문지B
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• 제29B권2호
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• pp.1-8
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• 1992

This paper is proposed a Modified WLD (Weighted Levenshtein Distance) algorithm for processor desihn of code-string matching. A proposed MWLD (Modified Weighted Levenshtein Distance) algorithm is consist of 1-dimension bit-serial array processor to pattern matching using a Hamming Distance. The proposed processor is applied to recognition of character with real time input. The recognition rate of Hangul strokes is resulted to 98.65$\%$

• 한국항해학회지
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• 제14권4호
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• pp.31-39
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• 1990

A systematic methodology for efficient implementation of processor arrays from regular iterative algorithms is proposed. One of the modern parallel processing array architectures is the Systolic arrays and we use it for processor arrays on this paper. On designing the systolic arrays, there are plenty of mapping functions which satisfy necessary conditions for its implementation to the time-space domain. In this paper, we sue a few conditions to reduce the total number of computable mapping functions efficiently. As a results of applying this methodology, efficient designs of systolic arrays could be done with considerable saving on design time and efforts.

• 지질공학
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• 제5권1호
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• pp.95-103
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• 1995

이 논문은 적응 복합 어레이 처리기에 공간과 주파수 영역에 미분 영점 조건을 사용한 개조복합 어레이 처리기에 대하여 서술한다. 방해신호와 원하는 신호의 주파수는 같으나 방향은 서로 다르며, 방해신호의 방향가 주파수는 알고 있다고 가정하였다. 컴퓨터 실험 결과, 고계의 미분영점은 영점 폭을 넓게 하여 광대역 방해신호를 제거하는데 적합하며, 주파수 영역에서의 영계의 미분영점 (단순점 영점)은 복합어레이 처리기에 내재하는 여분의 오류 신호를 줄여 어레이의 성능을 향상시킬 수 있음이 판명되었다.

• 한국정보처리학회논문지
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• 제5권8호
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• pp.1985-1996
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• 1998

본 논문에서는 행렬 또는 벡터 곱셈을 선형 프로세서나 VLIW 시뮬레이터로 분할 및 배치하는 알고리즘을 제안한다. 먼저 입력 행렬이나 벡터를 임의 크기의 프로세서 배열에 배치하는 기법에 대해 논의하고, 문제 크기를 프로세서 배열 크기로 분할하는 알고리즘을 보인다. 이 알고리즘을 VLIW 시뮬레이터 상에서 실행하고 알고리즘의 효율성을 보이도록한다. 그 결과 우리가 설계한 VLIW 시뮬레이터 상에서의 수행이 선형 프로세서 상에서 보다 병렬화 성능이 향상됨을 알 수 있었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.603-604
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• 2008

This paper implemented The LED illuminance control IP based on 8bit RISC Processor. 8bit RISC Processor designed hardware interrupts, an interface for serial communications, a timer system with compare-capture-reload resources and a watchdog timer. LED Array consists of Red, Green, Blue, White and Warm White. The illuminance control IP is used to LED Board control with 8bit data.