• Journal of Power Electronics
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• v.7 no.2
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• pp.174-180
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• 2007

In this paper, a simple control method for two-stage utility grid-connected photovoltaic power conditioning systems (PCS) is proposed. This approach enables maximum power point (MPP) tracking control with post-stage inverter current information instead of calculating solar array power, which significantly simplifies the controller and the sensor. Furthermore, there is no feedback loop in the pre-stage converter to control the solar array voltage or current because the MPP tracker drives the converter switch duty cycle. This simple PCS control strategy can reduce the cost and size, and can be utilized with a low cost digital processor. For verification of the proposed control strategy, a 2.5kW two-stage photovoltaic grid-connected PCS hardware which consists of a boost converter cascaded with a single-phase inverter was built and tested.

• The KIPS Transactions:PartA
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• v.10A no.4
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• pp.389-396
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• 2003

InfiniBand technology is being accepted as the future system interconnect to serve as the high-end enterprise fabric for cluster computing. This paper presents the design and implementation of the InfiniBand system interconnect, focusing on an InfiniBand host channel adapter (HCA) based on dual ARM9 processor cores The HCA is an SoC tailed KinCA which connects a host node onto the InfiniBand network both in hardware and in software. Since the ARM9 processor core does not provide necessary features for multiprocessor configuration, novel inter-processor communication and interrupt mechanisms between the two processors were designed and embedded within the KinCA chip. Kinch was fabricated as a 564-pin enhanced BGA (Bail Grid Array) device using 0.18${\mu}{\textrm}{m}$ CMOS technology Mounted on host nodes, it provides 10 Gbps outbound and inbound channels for transmit and receive, respectively, resulting in a high-performance cluster system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.5A
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• pp.284-293
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• 2003

Location service is usually provided by the GPS method using satellites. In the next generation mobile communication systems which use smart antennas, location service can be accomplished using direction of arrival (DOA) estimation techniques. In this paper, we propose a DOA estimation technique for the location service of the next generation mobile communication systems and investigate the validity of the proposed technique through computer simulation. First, DOA estimation problems of distributed sources are considered using vortical and horizontal array processors which are orthogonal to each other. The DOA of the elevation angle is estimated by the vertical array processor and then that of the azimuth angle is estimated by the horizontal array processor. Finally, the procedures of the location service for specific signal sources using three smart antennas are exhibited by computer simulation to show that the proposed DOA estimation technique can be used for the location service in the next generation mobile communication systems.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.259-266
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM (or SRAM) cell. Layout pitch of one-bit-wide logic is Identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1) simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.101-108
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• 2007

Parallel processing algorithms, coupled with advanced networking and distributed computing architectures, improve the overall computational performance, dependability, and versatility of a digital signal processing system In this paper, novel parallel algorithms are introduced and investigated for advanced sonar algorithm, conventional matched-field processing (CMFP). Based on a specific domain, each parallel algorithm decomposes the sequential workload in order to obtain scalable parallel speedup. Depending on the processing requirement of the algorithm, the computational performance of the parallel algorithm reveals different characteristics. The high-complexity algorithm, CMFP shows scalable parallel performance on the array of DSP processors. The impact on parallel performance due to workload balancing, communication scheme, algorithm complexity, processor speed, network performance, and testbed configuration is explored.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.4
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• pp.424-434
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• 2015

Adaptive beamforming algorithms have been widely used to remove interference and jamming in the phased array radar system. Advances in the field programmable gate array(FPGA) technology now make possible the real time processing of adaptive beamforming (ABF) algorithm. In this paper, the FPGA based real-time implementation method of adaptive beamforming system(beamformer) in the pre-processor module for active electronically scanned array(AESA) radar is proposed. A compact FPGA-based adaptive beamformer is developed using commercial off the shelf(COTS) FPGA board with communication via OpenVPX(Virtual Path Cross-connect) backplane. This beamformer comprises a number of high speed complex processing including QR decomposition & back substitution for matrix inversion and complex vector/matrix calculations. The implemented result shows that the adaptive beamforming patterns through FPGA correspond with results of simulation through Matlab. And also confirms the possibility of application in AESA radar due to the real time processing of ABF algorithm through FPGA.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• 대한공업교육학회지
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• v.31 no.1
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• pp.185-199
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• 2006

In this paper, to detect lateral direction sound pressure fiber optic sensor using Fabry-Perot interferometeric sensor array was fabricated and experimented. This parallel sensor array composed of one light source and the light split into each sensor using directional coupler and to see the output signal the array system do not need any digital signal processor. As a lateral direction sound source arbitrary sound frequency of 100Hz, 200Hz, and 655Hz using by nondirectional speaker were applied to the array sensor which installed on $60cm{\times}60cm{\times}60cm$ latticed structure. The detected signals from the two sensors were analyzed in the time and frequency domains. It was confirmed that the suggested sensor array detected applied sound source well but there were a little amplitude differences in between the sensors. Because the sensor supported simply at both ends theoretical analysis was performed and its solution was suggested. To compare the theoretical and experimental results arbitrary sound frequency of 2kHz was applied to the sensor array. It shows that experimental results was good agreement with theoretical results.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.11a
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• pp.255-258
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• 2004

The SAR(Solar Array Regulator) of KOMPSAT(Korea Multi Purpose SATellite)-1, 2 regulates a photovoltaic power according to the duty ratio commands of the ECU. But the ECU has so many other jobs that it can not calculate the solar array condition immediately. It means the SAR cannot always generate the maximum power of a photovoltaic. Nowadays, the commercial photovoltaic systems are using a controller operated by digital processing. But the usage for satellite is not adaptable. It is not easy to find the processor of the space grade and the price is expensive. So in this paper, the simple analog MPPT(Maximum Power Point Tracking) algorithm is proposed for the small satellite in LEO. This algorithm does not need any calculation of power by multiplication of voltage and current md a measurement of the solar array temperature. It is consist of only two sample and hold circuits, two comparators, a flip-flop, and an integrator. The proposed MPPT algorithm is verified by the simulation and experimental.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.29-35
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• 1998

This paper describes architectures and design of a SIMD type parallel image processing chip called SliM-II. The chiphas a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives at least 1.92 GIPS. In contrast to existing array processors, such as IMAP, MGAP-2, VIP, etc., each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU operation, data I/O, and inter-PE communication simulataneously in a single instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel move between the register file and on-chip memory as in DSP chips, SliM-II can greatly reduce the inter-PE communication overhead, due to the idea a sliding, which is a technique of overlapping inter-PE communication with computation. Moreover, the bandwidth of data I/O and inter-PE communication increases due to bit-parallel data paths. We used the COMPASS$^{TM}$ 3.3 V 0.6.$\mu$m standrd cell library (v8r4.10). The total number of transistors is about 1.5 muillions, the core size is 13.2 * 13.0 mm$^{2}$ and the package type is 208 pin PQ2 (Power Quad 2). The performance evaluation shows that, compared to a existing array processors, a proposed architeture gives a significant improvement for algorithms requiring multiplications.s.