• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.24-32
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM(or SRAM) cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1)simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering, like smoothing and segmentation, may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.2
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• pp.227-236
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• 2001

This paper proposes a frequency-domain partially adaptive algorithm, called a censoring algorithm, to reduce the computational complexity of the frequency domain adaptive array. The proposed censoring algorithm determines the existence of interferences in the frequency-domain at each frequency bin using a constant false alarm rate (CFAR) processor. The censoring algorithm adapts only those parts of the weights that correspond to the frequency bins expected to contain interferences. The censoring algorithm is also expanded to overcome the signal cancellation phenomenon caused by smart jammers. Accordingly, a censoring spatial smoothing, which combines the censoring algorithm with spatial smoothing, is proposed. Simulation results show that the proposed algorithms are effective in removing interferences with only part of the computational complexity of conventional algorithms yet with the same level of performance.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.285-288
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• 2005

We propose a novel programmable miniature vision module based on a custom designed analog VLSI (aVLSI) chip. The vision module consists of the optical flow vision sensor embedded with commercial off-the-shelves digital hardware; in our case is the Intel XScale PXA270 processor enforced with a programmable gate array device. The aVLSI sensor provides gray-scale imager data as well as smooth optical flow estimates, thus each pixel gives a triplet of information that can be continuously read out as three independent images. The particular computational architecture of the custom designed sensor, which is fully parallel and also analog, allows for efficient real-time estimations of the smooth optical flow. The Intel XScale PXA270 controls the sensor read-out and furthermore allows, together with the programmable gate array, for additional higher level processing of the intensity image and optical flow data. It also provides the necessary standard interface such that the module can be easily programmed and integrated into different vision systems, or even form a complete stand-alone vision system itself. The low power consumption, small size and flexible interface of the proposed vision module suggests that it could be particularly well suited as a vision system in an autonomous robotics platform and especially well suited for educational projects in the robotic sciences.

• Journal of Korea Multimedia Society
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• v.11 no.10
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• pp.1460-1470
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• 2008

As the performance of recent mobile systems increases, a vector graphic has been implemented to represent various types of dynamic menus, mails, and two-dimensional maps. This paper proposes a hardware accelerator for open vector graphics (OpenVG), which is widely used for two-dimensional vector graphics. We analyze the specifications of an OpenVG and divide the OpenVG into several functions suitable for hardware implementation. The proposed hardware accelerator is implemented on a field programmable gate array (FPGA) board using hardware description language (HDL) and is about four times faster than an Alex processor.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.142-146
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• 2012

Today, the demand for high-speed data communication and mobile communication has exploded. Thus, there is a growing need for optical communication systems that convert large volumes of data to optical signals and that accommodate and transmit the signals across long distances. Digital optical communication with these characteristics consists of a master unit (MU) and a slave unit (SU). However, the digital optical units that are currently commercialized or being developed transmit data without compression. Thus, digital optical communication using these units is restricted by the quantity of optical frames when adding diversity or operating with various combinations of CDMA, WCDMA, WiBro, GSM, LTE, and other mobile communication technologies. This paper suggests the application of a data compression algorithm to a digital signal processor (DSP) chip as a field programmable gate array (FPGA) and a complex programmable logic device (CPLD) of a digital optical unit to add separate optical waves or to transmit complex data without specific changes in design of the optical frame.

• Journal of Broadcast Engineering
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• v.18 no.5
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• pp.669-679
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• 2013

This paper proposed a new VLSI (Very Large Scale Integrated Circuit) architecture for stereo matching in real time. We minimized the amount of calculation and the number of memory accesses through analyzing calculation of stereo matching. From this, we proposed a new stereo matching calculating cell and a new hardware architecture by expanding it in parallel, which concurrently calculates cost function for all pixels in a search range. After expanding it, we proposed a new hardware architecture to calculate cost function for 2-dimensional region. The implemented hardware can be operated with minimum 250Mhz clock frequence in FPGA (Field Programmable Gate Array) environment, and has the performance of 805fps in case of the search range of 64 pixels and the image size of $640{\times}480$.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.34 no.1
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• pp.11-19
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• 2024

The increased utilization of the FFT in signal processing, cryptography, and various other fields has highlighted the importance of optimization. In this paper, we propose the implementation of an accelerator that processes the radix-2 16 points FFT algorithm more rapidly and efficiently than FFT implementation of existing studies, using FPGA(Field Programmable Gate Array) hardware. Leveraging the hardware advantages of FPGA, such as parallel processing and pipelining, we design and implement the FFT logic in the PL (Programmable Logic) part using the Verilog language. We implement the FFT using only the Zynq processor in the PS (Processing System) part, and compare the computation times of the implementation in the PL and PS part. Additionally, we demonstrate the efficiency of our implementation in terms of computation time and resource usage, in comparison with related works.

• Journal of the Society of Naval Architects of Korea
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• v.50 no.3
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• pp.190-198
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• 2013

In order to predict acoustic pressure distributions by exterior incident wave at Cylindrical Hydrophone Array (CHA) sensor's positions, acoustic pressure analysis is performed by using beam tracing method. Beam tracing method is well-known of reliable pressure analysis methods at high-frequency range. When an acoustic noise source is located at the center of rectangular room, acoustic pressure analysis is performed by using both beam tracing method and Power Flow Boundary Element Method (PFBEM). By comparing with results of beam tracing method and those of PFBEM, the accuracy of beam tracing method is verified. We develop the CHA pressure analysis program by verified beam tracing method. The developed software is composed of model input, sensor array creator, analysis option, solver and post-processor. We can choose a model option of 2D or 3D. The sensor array generator is connected to a sonar which is composed of center position, bottom, top and angle between sensors. We also can choose an analysis option such as analysis frequency, beam number, reflect number, etc. The solver module calculates the ray paths, acoustic pressure and result of generating beams. We apply the program to 2D and 3D CHA models, and their results are reliable.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.10
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• pp.144-155
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• 1998

The array weights that will maximize the SNR for any type of noise environment are determined by the function of the antenna design configuration and the directions of receiving target and interference signals. The conventional SLCs(sidelobe cancellers) using the SNR maximization perform worst from the saturation of the receiving system of main channel when the main antenna has pattern with high gain at the arrival angle of strong interference. In this paper, the new SLC is accomplished by using two independent antenna architecture. Main antenna is implemented with adaptive nulling, which is used for rejecting high-power interference primarily. Auxiliary antenna is realized with adaptive array for receiving interference signal to be suppressed completely, which has a characteristics of sufficient gain for every direction. The new SLC is implemented with above both antennas. We show that the new SLC, which consists of the adaptive nulling main antenna and the adaptive array auxiliary antenna, is useful in reducing the effect of strong interference like jammer, because the adaptive nulling at main antenna prevents its receiver and signal processor for saturation by strong interference. The proposed SLC has improved SNR over the conventional SLCs. The improved SNR at sidelobe region is typically more than 7 dB for a given test signal. Moreover, it improves the SNR of about 20 dB under strong interference at mainlobe.

• The Journal of the Acoustical Society of Korea
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• v.25 no.7
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• pp.346-355
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• 2006

Acoustic data from a shallow water experiment in the East Sea of Korea (MAPLE IV) is Processed to investigate the Performance of matched-field geo-acoustic inversion and source localization. The receiver array consists of two legs as in an L-shape. one vertical and the other horizontal lying on the seabed. Narrowband multi-tone CW source was towed along a slightly inclined bathymetry track. The matched-field geo-acoustic inversion includes comparisons between three processing techniques. all based on the Bartlett processor as; (1) the coherent processing of the data from the full array, (2) the incoherent Product of each output from both the horizontal and vertical arrays, and (3) the cross correlation between the horizontal and vertical arrays. as well as processing each array leg separately. To verify the inversion results. matched-field source localization for low level source signal components were performed using the same Processors used at the inversion stage.