• 한국철도학회:학술대회논문집
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• 한국철도학회 2006년도 추계학술대회 논문집
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• pp.1320-1325
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• 2006

Railway track supports and guides train and it directly affects ride quality and safety. To maintain track quality, regular maintenance activity is essential but it degrades track usage since maintenance activity occupies the track during the work. To achieve maximum track efficiency, track inspection should be performed at commercial running speed. In this paper, we designed and developed high speed rail profile measurement system using laser light sectioning method with line laser generator, digital camera and DSP based image processing system. The measurement system can supports rail profile measurement at the speed of 300 Km/h that can be applied to KTX.

• 한국정보처리학회논문지
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• 제7권2호
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• pp.437-445
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• 2000

마이크로셀룰러 네트워크에서 재사용 분할 시스템은 고속 단말의 핸드오프 증가로 시스템 성능이 저하되는 단점을 갖는다. 따라서 본 논문에서는 마이크로셀을 이용한 재사용 분할 시스템의 성능을 개선하기 위하여 내부셀과 외부셀의 트래픽 분포 비율에 따라 고속과 저속 단말의 자원을 관리하는 핸드오프 알고리즘을 제안한다. 또한 고속과 저속 단말의 성능을 분석하고 컴퓨터 시뮬레션을 통해서 핸드오프 확률, 호 절단 확률에 대하여 RPS와 비교 평가한다.

• 센서학회지
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• 제30권2호
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• pp.82-87
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• 2021

In this paper, we propose a high-speed, low-power complementary metal-oxide semiconductor (CMOS) binary image sensor featuring a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector based on a double-tail comparator. The GBT photodetector forms a structure in which the floating gate (n+ polysilicon) and body of the PMOSFET are tied, and amplifies the photocurrent generated by incident light. The double-tail comparator compares the output signal of a pixel against a reference voltage and returns a binary signal, and it exhibits improved power consumption and processing speed compared with those of a conventional two-stage comparator. The proposed sensor has the advantages of a high signal processing speed and low power consumption. The proposed CMOS binary image sensor was designed and fabricated using a standard 0.18 ㎛ CMOS process.

• 소성∙가공
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• 제33권2호
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• pp.87-95
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• 2024

The current study aims to prove that high-speed forming has better formability than conventional low-speed forming. Experimentally, the quasi-static forming limit diagram was obtained by Nakajima test, and the dynamic forming limit diagram was measured by electrohydraulic forming. For the experiments, the LS-DYNA was used to create the optimal specimen for electrohydraulic forming. The strain measurement was performed using the ARGUS, and comparison of the forming limit diagrams confirmed that EHF showed better formability than quasi-static forming. Theoretically, the Marciniak-Kuczynski model was used to calculate the theoretical forming limit. Swift hardening function and Cowper Symonds model were applied to predict the forming limits in quasi-static and dynamic status numerically.

• Journal of Biosystems Engineering
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• 제39권4호
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• pp.324-329
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• 2014

Purpose: The finite element method (FEM) is advantageous because it can save time and cost by reducing the number of samples and experiments in the effort to identify design factors. In computational problem-solving it is necessary that the exact material properties are input for achieving a reliable analysis. However, in the case of fiber boards, it is difficult to measure their cross-directional material properties because of their small thickness. In previous research studies, the Poisson's ratio was measured by analyzing ultrasonic wave velocities. Recently, the Poisson's ratio was measured using a high-speed digital camera. In this study, we measured the transverse strain of a fiber board and calculated its Poisson's ratio using a high-speed digital camera in order to apply these estimates to a FEM analysis of a fiber board, a corrugated board, and a corrugated box. Methods: Three different fiber board samples were used in a uniaxial tensile test. The longitudinal strain was measured using the Universal Testing Machine. The transverse strain was measured using an image processing method. To calculate the transverse strain, we acquired images of the fiber board before the test onset and before the fracture occurred. Acquired images were processed using the image processing program MATLAB. After the images were converted from color to binary, we calculated the width of the fiber board. Results: The calculated Poisson's ratio ranged between 0.2968-0.4425 (Machine direction, MD) and 0.1619-0.1751 (Cross machine direction, CD). Conclusions: This study demonstrates that measurement of the transverse properties of a fiber board is possible using image processing methods. Correspondingly, these processing methods could be used to measure material properties that are difficult to measure using conventional measuring methodologies that employ strain gauge extensometers.

• 한국인터넷방송통신학회논문지
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• 제10권6호
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• pp.113-118
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• 2010

주행 중인 자동차 타이어의 손상을 검출하기 위해 타이어에서 발생하는 초음파 신호에 대한 스플릿 스펙트럼 처리 알고리즘을 연구하였다. 스플릿 스펙트럼의 최대값을 추정하는 알고리즘을 사용하여 정상적인 타이어와 손상 물질에 의해 손상된 타이어에 대한 처리 결과를 비교하였다. 자기상관함수를 이용한 결과, 실험에 사용된 손상된 타이어에서는 주행속도 50km/h 일 때 162.9ms, 100km/h 일 때 84.81ms 주기로 손상 특이점을 검출 할 수 있었으며, 이에 의해 자동차 주행속도에 따른 손상 특징 점의 주기성을 이용하여 손상 물질에 의한 타이어의 손상 판단이 가능하였다.

• 대한전자공학회논문지
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• 제20권2호
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• pp.7-15
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• 1983

근년, 반도체 기술의 급격한 진보에 따라 고기능 논리회로의 VLSI화가 가능하게 되었다. 이에 따라 수치 처리의 고원화, 광대역 화상처리등을 위한 고기능 회로들의 전용 VLSI 칩의 설계가 연구되고 있으며, 여러 종류의 소프트웨어 패키지의 VLSI화가 가능하게 되었다. 본 논문에서는 계산기의 회귀분석용 범용 소프트웨어 패키지(BMD)를 하드웨어화하는 설계 수법을 제안하였다. 이것은 종래의 통계 처리를 소프트웨어에만 의존하기 때문에 처리 속도가 저하되는 것을 하드웨어화함으로써 개선하였다. 설계 알고리즘은 통계 수첩의 계산 특징을 살려 본 시스템을 구성한다. 그 결과 하드웨어화에 의하여 소프트웨어 패키지의 복잡성이 제거되고, 고속 처리함으로써 확률을 향상시켰다.

• 융합신호처리학회논문지
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• 제9권3호
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• pp.224-229
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• 2008

In the paper, a new Constraint algorithm is proposed to solve the fan-in problem occurred in the encoding circuitry of an ADC. The Flash ADC architecture uses a Double-Base Number System(DBNS). The DBNS has been known to represent the Multidimensional Logarithmic Number System (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in Digital Signal Processing (DSP) applications. The authors use the DBNS with the base 2 and 3 in designing ADC encoder circuits, which is called as Double Base Integer Encoder(DBIE). A symmetric map is analyzed first, and then asymmetric map is followed to provide addition ready DBNS for DSP circuitry. The simulation results of the DBIE circuits in 6-bit and 8-bit ADC show the effectiveness of the Constraint algorithm with $0.18{\mu}m$ CMOS technology. The DBIE yields faster processing speed compared to the speed of Fat Tree Encoder (FAT) circuits by 17% at more power consumption by 39%.

• 제어로봇시스템학회논문지
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• 제9권7호
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• pp.498-506
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• 2003

A computer vision system applied to an intelligent safety vehicle has been required to be worked on a small sized real time special purposed hardware not on a general purposed computer. In addition, the system should have a high reliability even under the adverse road traffic environment. This paper presents a design and an implementation of an onboard hardware system taking into account for high speed image processing to analyze a road traffic scene. The system is mainly composed of two parts: an early processing module of FPGA and a postprocessing module of DSP. The early processing module is designed to extract several image primitives such as the intensity of a gray level image and edge attributes in a real-time Especially, the module is optimized for the Sobel edge operation. The postprocessing module of DSP utilizes the image features from the early processing module for making image understanding or image analysis of a road traffic scene. The performance of the proposed system is evaluated by an experiment of a lane-related information extraction. The experiment shows the successful results of image processing speed of twenty-five frames of 320$\times$240 pixels per second.

• Journal of Information Processing Systems
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• 제7권3호
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• pp.531-542
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• 2011

In this paper, we propose a new congestion control scheme for high-speed networks. The basic idea of our proposed scheme is to adopt a game theory called, "Minority Game" (MG), to realize a selective reduction of the transmission speed of senders. More concretely, upon detecting any congestion, the scheme starts a game among all senders who are participating in the communication. The losers of the game reduce the transmission speed by a multiplicative factor. MG is a game that has recently attracted considerable attention, and it is known to have a remarkable property so that the number of winners converges to a half the number of players in spite of the selfish behavior of the players to increase its own profit. By using this property of MG, we can realize a fair reduction of the transmission speed, which is more efficient than the previous schemes in which all senders uniformly reduce their transmission speed. The effect of the proposed scheme is evaluated by simulation. The result of simulations indicates that the proposed scheme certainly realizes a selective reduction of the transmission speed. It is sufficiently fair compared to other simple randomized schemes and is sufficiently efficient compared to other conventional schemes.