• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.74-82
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• 2015

As the complexity of an electronic device and the reduction of its operating voltage is progressing, susceptibility test of the chip and module for internal or external noises is essential. Although the immunity compliance of the chip was served with IEC 62132-4 Direct Power Injection method as an industry standard, in fact, EM immunity of the chip is influenced by their Power Domain Network (PDN). This paper evaluates the EM noise tolerance of a PLL and compares their noise transfer characteristics to the PLL on various PCB boards. To make differences of the PDNs of PCBs, various PCBs with or without LDO and with several types of capacitors are tested. For evaluation of discrepancies between EM characteristics of an IC only and the IC on real boards, the analysis of the noise transfer characteristics according to the PDNs shows that it gives important information for the design having robust EM characteristics. DPI measurement results show that greatly improved immunity of the PLL in the low-frequency region according to using the LDO and a frequency change of the PLL according to the DPI could also check with TEM cell measurement spectrum.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.376-383
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• 2008

Generally a return current plane(RCP) of high speed digital and analog part is partitioned. This is achieved in order to decrease the noise interference between subsystem in PCBs(Printed Circuit Boards). However, when the connected signal line exists between each subsystem, this partition will cause unwanted effects. In a EMI(Electromagnetic Interference) point of view, the partition of the return current plane becomes a primary factor to increase the radiated emission. Component bridge(CB) is used for the way of maintaining radiated emission, still specific user's guide doesn't give sufficient principle. In a view point of EMI, design principle of multi-CB using method will be analyzed by measurement. And design principle of noise mitigation will be provided. Generally interval of multi-CB is ${\lambda}/20$ ferrite bead. In this study, When multi-CB connection is applied, design principle of ferrite bead and chip resistor is proved by measurement. Multi-connected chip resistance$(0{\Omega})$ is proved to be more effective design method in the point of EMI.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.7
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• pp.1048-1056
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• 2001

Decoupling capacitors are commonly used to reduce the effect of SSN propagated through parallel power and ground planes in high-speed multilayer printed circuit boards (PCBs). In this paper, we introduced a simple high frequency measurement and proposed a wideband (50 MHz ∼3 GHz) equivalent circuit model for decoupling capacitor considering high frequency parasitic effects. The proposed model can be easily combined with the SPICE model of power supply planes far SSN analysis. The circuit simulations with the proposed model show good agreement with the measurement results. Also, we expect to accurately analyze the noise reduction effect as a function of value and location using the proposed model of decoupling capacitor.

• Journal of Advanced Navigation Technology
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• v.28 no.1
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• pp.129-135
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• 2024

In this paper, an analytical approach for the design and analysis of an aperiodic electromagnetic bandgap (EBG)-based power distribution network (PDN) in high-speed integrated-circuit (IC) packages and printed circuit boards (PCBs) is proposed. Aperiodic EBG is an effective method to solve the noise problem of high-speed IC packages and PCBs. However, its analysis becomes challenging due to increased computation time. To overcome the problem, the proposed analytical method entails deriving impedance parameters for EBG island and the overall PDN, which includes locally placed EBG structures. To validate the proposed method, a test vehicle is fabricated, demonstrating good agreement with the measurements. Significantly, the proposed analytical method reduces computation time by 99.7 %compared to the full-wave simulation method.

• Resources Recycling
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• v.21 no.3
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• pp.56-64
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• 2012

It is generally well known that PCB (Printed Circuit Board) is an electric component assembled by various metals mixed with plastics and ceramics. Accordingly, it is very important to extract metallic components from used PCBs from the point of view of recycling of used resources as well as an environmental protection. In this paper, patents and paper on the recycling technologies of PCB were analyzed. The range of search was limited in the open patents of USA (US), European Union (EP), Japan (JP), Korea (KR) and SCI journals from 1980 to 2011. Patents and journals were collected using key-words searching and filtered by filtering criteria. The trends of the patents and journals was analyzed by the years, countries, companies, and technologies.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.2
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• pp.55-60
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• 2002

The recent trend in electronic devices has been towards light weight, low cost, high performance and improved reliability. Passive components are very important parts of microelectronic devices. The number of passive components used in hand held devices and computers continue to increase. To achieve improvements in costs, component density, performance, and reliability, embedding of these passive components into the printed circuit boards (PCBs) is required. This paper introduces the embedding of passive components, and discusses the remained challenges in the commercialization of this technique.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.8
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• pp.995-1000
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• 1999

This paper presents a optic system and a visual inspection algorithm looking for solder joint defects of J-lead chip which are more integrate and smaller than ones with Gull-wing on PCBs(Printed Circuit Boards). The visual inspection system is composed of three sections : host PC, imaging and driving parts. The host PC part controls the inspection devices and executes the inspection algorithm. The imaging part acquires and processes image data. And the driving part controls XY-table for automatic inspection. In this paper, the most important five features are extracted from input images to categorize four classes of solder joint defects in the case of J-lead chip and utilized to a back-propagation network for classification. Consequently, good accuracy of classification performance and effectiveness of chosen five features are examined by experiment using proposed inspection algorithm.

• Journal of the Korean Society for Precision Engineering
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• v.15 no.7
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• pp.26-35
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• 1998

This paper presents a visual inspection algorithm looking for solder joint defects of IC chips on PCBs (Printed Circuit Boards). In this algorithm, seven features are proposed in order to categorize the solder joints into four classes such as normal, insufficient, excess, and no solder, and optimal back-propagation network is determined by error evaluation which depend on the number of neurons in hidden and out-put layers and selection of the features. In the end, a good accuracy of classification performance, an optimal determination of network structure and the effectiveness of chosen seven features are examined by experiment using proposed inspection algorithm.

• Journal of Advanced Navigation Technology
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• v.28 no.2
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• pp.246-249
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• 2024

In this paper, we present a miniaturized differential line (DL) using inductance-enhanced corrugated ground planes (LCGP) for effective common-mode (CM) noise suppression in high-speed packages and printed circuit boards. The LCGP-DL demonstrates the CM noise suppression in the frequency range from 2.09 GHz to 3.6 GHz. Furthermore, to achieve the same low cutoff frequency, the LCGP-DL accomplishes a remarkable 23.2% reduction in size compared to a reference DL.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.2
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• pp.43-50
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• 2009

Although thin PCBs(Printed Circuit Boards) have recently been required for high density interconnection, high electrical performance, and low manufacturing cost, the utilization of thin PCBs is severely limited by warpage and reliability issues. Warpage of the thin PCB leads to failure in solder-joints and chip. The $B^2it$(Buried Bump Interconnection Technology) for PCB has been developed to achieve a competitive manufacturing price. In this study, chip temperature, package warpage, chip stress and solder-joints stress characteristics of the PCB prepared with $B^2it$ process have been calculated using thermo-mechanical coupled analysis by the FEM(Finite Element Method). FEM computation was carried out with the variations in bump shapes and kinds of materials under 1.5W power of chip and constant convection heat transfer. The results show that chip temperature distribution reached more quickly steady-state status with PCB prepared with $B^2it$ process than PCB prepared with conventional via interconnection structure. Although $B^2it$ structures are effective on low package warpage and chip stress, with high strength bump materials arc disadvantage for low stress of solder-joints. Therefore, it is recommended that optimized bump shapes and materials in PCB design should be considered in terms of reliability characteristics in the packaging level.