• Aerospace Engineering and Technology
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• v.9 no.1
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• pp.1-8
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• 2010

The tilt-rotor Smart UAV(Unmanned Air Vehicle) has been developed by KARI(Korea Aerospace Research Institute) for civil purposes. In order to prove the reliabilities of total system of Smart UAV, the series of ground tests were performed including system interface test, aircraft HILS(Hardware In the Loop Simulation) Test, ground power test, 4-DOF (Degrees of Freedom)rig test, and tethered hover test. Many unexpected problems occurred at each ground test. With clearing these problems, the total Smart UAV systems were matured and the airworthiness was proven enough. After complete of additional ground test proposed by FRRB(Flight Readiness Review Board), the first flight test will be performed in this year. This paper presents the procedures and the analysis results of the ground tests for the tilt-rotor Smart UAV.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.9
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• pp.114-129
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• 1996

This paper describes the whole development phase for the underwater vehicle actuating system with high hydroload torque disturbance. This includes requirement analysis, system modeling, control algorithm design, real time implementation, test and performance evaluations. As for driving control algorithms, fuzzy logic, variable structure and PD(Proportional-Differential) algorithm were designed and implemented on board controller using a single chip microprocessor. Intel 8797. And test and performance evaluation is carried out both single test and wystem integration test. We could confirm the basic performance of actuating system through the single test and gereral developing work of any actuating systems was finished with a single performance test of actuating system without system integration test. But, we suggested that system integration test be needed. System integration test is carried out using G/C HILS(Guidance and Control Hardware-In-the -Loop Simulation) which is constituted flight motion simulator, load simulator, real time host computer and the related subsystems such as inertial navigation system, power supply system and Guidance and Control Computer etc.. The most important practical contribution of this paper is that full system characteristics such as minimal control effort, enhancement of guidance and autopilot performance by the actuating system using G/C HILS technique are investigated. Through full running G/C HILS, in spite of the passing to single tests, some control algorithm resulted in failure as to stability of full system and system time frame.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.19-24
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• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.61-70
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• 2016

This paper describes a new PMU(parametric measurement unit) design technique for automatic test equipment(ATE). Only one DDA(differential difference amplifier) is used to force the test signals to DUT(device under test), while conventional design uses two or more amplifiers to force test signals. Since the proposed technique does not need extra amplifiers in feedback path, the proposed PMU inherently guarantees stable operation. Moreover, to measure the response signals from DUT, proposed technique also adopted only one DDA amplifier as an IA(instrument amplifier), while conventional IA uses 3 amplifiers and several resistors. The DDA adopted two rail-to-rail differential input stages to handle full-range differential signals. Gain enhancement technique is used in folded-cascode type DDA to get open loop gain of 100 dB. Proposed PMU design enables accurate and stable operation with smaller hardware and lower power consumption. This PMU is implemented with 0.18 um CMOS process and supply voltage is 1.8 V. Input ranges for each force mode are 0.25~1.55 V at voltage force and 0.9~0.935 V at current force mode.