• Journal of electromagnetic engineering and science
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• v.5 no.2
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• pp.92-96
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• 2005

This paper presents a novel microwave oscillator incorporating a simple microstrip ring type resonant cell as its terminating resonance component. Reduced chip size, higher dc-ac power efficiency, superior harmonic characteristics can be achieved from the introduction of a compact microstrip ring resonator cell. The oscillator provides a second harmonic suppression of 26.51 dB and the output power of 2.046 dBm at 2.11 GHz.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.116-119
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• 2005

In this paper, we propose the PLL system of the local oscillator system for the millimeter wave band's radio astronomy receiving system. The development of the proposed local oscillator system based on the YIG oscillator VCO with 26.5 ${\sim}$ 40GHz specification. This system consists of the oscillator part including the YIG VCO, the harmonic mixer, and the isolator, the RF processing part including the triplexer, limiter, and RF discrimination processor. and the PLL system including YIG modulator and controller. Based on this configuration. we verify the frequency and power stability of the developed local oscillator system according to some temperature variation. From this test results we confirm the stable output frequency and power characteristic performance of the developed La system at constant temperature.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.441-446
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• 2008

In this papers, a PLDRO(Phase Locked Dielectric Resonator Oscillator) is designed and implemented at the oscillator in which fundamental frequency is 18.3 GHz. The proposed PLDRO so as to improve the PLDRO of the general structure is designed to the goal of the minimize of the size and the performance improvement. Three VCO(Voltage controlled Oscillator) and the power combiner improved the output power. A VCDRO(Voltage Controlled Dielectric Resonator Oscillator) is manufactured using a varactor diode to tune oscillating frequency electrically, and its phase is locked to reference frequency by SPD(Sampling Phase Detector). This product is fabricated on Teflon substrate with dielectric constant 2.2 and device is ATF -13786 of Ka-band using. This PLDRO generates an output power of 5.67 dBm at 18.3 GHz and has the characteristics of a phase noise of -80.10 dBc/Hz at 1 kHz offset frequency from carrier, the second harmonic suppression of -33 dBc. The proposed PLDRO can be used in Ka-band satellite applications

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.625-626
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• 2006

An Ultra low power super-regenerative oscillator was implemented with on-chip inductor and quench signal generator. The super-regenerative oscillator detects the signal level as low as -70dBm while consuming only 0.48mA at 1.5V supply voltage. These results indicate that the super-regenerative oscillator can be outstanding candidate the simple, ultra low power receiver design.

• Journal of electromagnetic engineering and science
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• v.11 no.3
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• pp.161-165
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• 2011

In this paper, a high-efficiency DC-AC converter is used for wireless energy transmission. The DC-AC convertter is implemented by combining the oscillator and power amplifier. Given that the conversion efficiency of a DC-AC converter is strongly affected by the efficiency of the power amplifier, a high-efficiency power amplifier is implemented using a class-E amplifier structure. Also, because of the low output power of the oscillator connected to the input stage of the power amplifier, a high-gain two-stage power amplifier using a drive amplifier is used to realize a high-output power DC-AC converter. The high-efficiency DC-AC converter is realized by connecting the oscillator to the input stage of the high-gain high-efficiency two-stage class-E power amplifier. The output power and the conversion efficiency of the DC-AC converter are 40.83 dBm and 87.32 %, respectively, at an operation frequency of 13.56 MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.591-600
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• 2010

In this paper, three kinds of 24 GHz low-power CMOS cross-coupled voltage controlled oscillators are designed and fabricated for a short-range radar applications using TSMC 0.13 ${\mu}m$ CMOS process. The basic CMOS crosscoupled voltage controlled oscillator is designed for oscillating around a center frequency of 24.1 GHz and subthreshold oscillators are developed for low power operation from it. A double resonant circuit is newly applied to the subthreshold oscillator to improve the problem that parasitic capacitance of large transistors in a subthreshold oscillator can push the oscillation frequency toward lower frequencies. The fabricated chips show the phase noise of -101~-103.5 dBc/Hz at 1 MHz offset, the output power of -11.85~-15.33 dBm and the frequency tuning range of 475~852 MHz. In terms of power consumption, the basic oscillator consumes 5.6 mW, while the subthreshold oscillator does 3.3 mW. The subthreshold oscillator with the double resonant circuit shows relatively lower power consumption and improved phase noise performance while maintaining a comparable frequency tuning range. The subthreshold oscillator with double resonances has FOM of -185.2 dBc based on 1 mW DC power reference, which is an about 3 dB improved result compared with the basic oscillator.

• Journal of Korea Society of Digital Industry and Information Management
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• v.19 no.2
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• pp.11-25
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• 2023

With the increasing advancement of VLSI technology, health care system is also developing to serve the humanity with better care. Therefore, biomedical implantable devices are one of the amazing important invention of scientist to collect data from the body cell for the diagnosis of diseases without any pain. This Biomedical implantable transceiver circuit has several important issues. Oscillator is one of them. For the design flexibility and complete transistor-based architecture ring oscillator is favorite to the oscillator circuit designer. This paper represents the design and analysis of the a 9-stage CMOS ring oscillator using cadence virtuoso tool in 180nm technology. It is also designed to generate the carrier signal of 403.5MHz frequency. Ring oscillator comprises of odd number of stages with a feedback circuit forming a closed loop. This circuit was designed with 9-stages of delay inverter and simulated for various parameters such as delay, phase noise or jitter and power consumption. The average power consumption for this oscillator is 9.32㎼ and average phase noise is only -86 dBc/Hz with the source voltage of 0.8827V.

• International journal of advanced smart convergence
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• v.10 no.1
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• pp.12-23
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• 2021

This paper proposes a low power radio frequency receiver front-end where, in a single stage, single-balanced mixer and voltage-controlled oscillator are stacked on top of low noise amplifier and re-use the dc current to reduce the power consumption. In the proposed topology, the voltage-controlled oscillator itself plays the dual role of oscillator and mixer by exploiting a series inductor-capacitor network. Using a 65 nm complementary metal oxide semiconductor technology, the proposed radio frequency front-end is designed and simulated. Oscillating at around 2.4 GHz frequency band, the voltage-controlled oscillator of the proposed radio frequency front-end achieves the phase noise of -72 dBc/Hz, -93 dBc/Hz, and -113 dBc/Hz at 10KHz, 100KHz, and 1 MHz offset frequency, respectively. The simulated voltage conversion gain is about 25 dB. The double-side band noise figure is -14.2 dB, -8.8 dB, and -7.3 dB at 100 KHz, 1 MHz and 10 MHz offset. The radio frequency front-end consumes only 96 ㎼ dc power from a 1-V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.8
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• pp.1297-1304
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• 2002

The phase locked oscillator having a low phase noise and high output in Ku-band was designed. To obtain the low phase noise and high output characteristics of oscillator, the nonlinear equivalent circuits of p-HEMT was analyzed by TOM method and we have decided the trade-off bias point between the low phase noise and the output power of oscillator. The designed phase locked oscillator with prescaler for stable operation, experiment results exhibits output power of 1003m with phase noise in the phase locked state of -824BC/HB at 10mz offset from 13.250Hz, and simulation result of 1003m output power in the phase noise -840Bc/Hz at 10KHz offset frequency respectively. a good agreement has been obtained between simulations and experiments results.

• Journal of Satellite, Information and Communications
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• v.1 no.1
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• pp.54-58
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• 2006

A new design for easily controlling operating frequency of an antenna-integrated planar oscillator is introduced. The oscillator circuit of a broadband negative-resistance active part and a passive load including a patch antenna. The patch resonance is used for determining the oscillation frequency. This design reduces the possibility of mismatch between antenna radiation and oscillation frequencies. To achieve optimum output power, load-pull simulation for the negative-resistance circuit is used. The load-pull simulation shows the feed point and the delay of feed line can affect the oscillation power. Two negative-resistance circuits capable of supporting oscillation over full C-band and X-band are fabricated. The oscillation frequency, output power and phase noise for different patch antennas are measured.