• Journal of the Korean Society of Food Science and Nutrition
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• v.44 no.12
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• pp.1865-1872
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• 2015

This study attempted to investigate consumer perceptions and attitudes towards reducing sugar intake by providing data to develop guidelines for the government and food-related industries to encourage Korean consumers to maintain appropriate levels of sugar intake. A survey was conducted on 238 adult consumers regarding their purchasing power for products with high sugar content in Seoul and Bundang, Gyeonggi area from September 1~30, 2013. Nutritional information on sugary products had a greater impact than media and others' recommendations on consumer awareness regarding need to reduce sugar intake. External factors such as health and weight control were stronger reasons for consuming reduced amounts of sugar or sugar-free products than internal factors such as sweetness. However, internal factors-such as taste-did not have a greater effect on consuming reduced amounts of sugar or sugar-free products than environmental factors-such as absence of purchase channels. Consumers indicated higher acceptance for 50% reduction in sweetness of existing commercial products. Regarding methods of lowering sugar intake, sugar replacement and reducing sugar consumption both generally and at home were preferred. In addition, consumers were likely to pay 10~14% more for sugar-reduced products than for existing products. Overall, consumers expressed positive attitudes towards reducing sugar intake in the future, although those in their twenties tended to be more passive than other age groups.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.