• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.34-43
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• 2008

An OpenLDI receiver circuit for flat-panel display systems was designed and fabricated using $1.8-{\mu}m$ high-voltage CMOS technology. Designed circuit roughly consists of DLL circuit and parallelizers, which recovers clock and parallelize data bits, respectably. It has one clock input and four data inputs. Measurement results showed that it successfully recovers clock signal from input whose frequency is $10Mhz{\sim}65Mhz$, which corresponds data rate of $70Mbps{\sim}455Mbps$ per channel, or $280Mbps{\sim}1.82Gbps$ when all of the four data channels were utilized. A commercial LCD monitor was modified into a test-bench and used for video data transmission at clock frequency of 49Mhz. In the experiment, power consumption was 19mW for core block and 82.5mW for output buffer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.28-33
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• 2008

This paper presents a continuous-time equalizer adopting a clock loss tracking technique for digital display interface. This technique uses bottom hold circuit to detect the incoming clock loss. The generated loss signal is directly fed to equalizer filters, building adaptive feed-forward loops which contribute the stability of the system. The design was done in $0.18{\mu}m$ CMOS technology. Experimental results summarize that eye-width of minimum 0.7UI is achieved until -33dB channel loss at 1.65Gbps. The average power consumption of the equalizer is a maximum 10mW, a very low value in comparison to those of previous researches, and the effective area is $0.127mm^2$.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.6
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• pp.87-93
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• 2008

This paper describes implementation of the 5.0GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.1*0.7mm^2$, and the chip area only core for IP in SoC is $1.0*0.4mm^2$. Through comparing and analysing of the designed two kind of the frequency synthesizer, we can conclude that if we improve a litter characteristics there is no problem to use their as IPs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.58-64
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• 2008

A 6Gbps 1:2 demultiplexer(DEMUX) IC using $0.18{\mu}m$ CMOS was designed and fabricated. For high speed performance current mode logic(CML) flipflop was used and inductive peaking technology was used so as to obtain higher speed than conventional Current mode logic flipflop. On-chip spiral inductor was designed to maximize the inductive peaking effect using stack structure. Total twelve inductors of $100{\mu}m^2$ area increase was used. The measurement was processed on wafer and 1:2 demultiplexer with and without micro stacked spiral inductors were compared. For 6Gbps data rate measurement, eye width was improved 7.27% and Jitter was improved 43% respectively. Power consumption was 76.8mW and eye height was 180mV at 6 Gbps

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.3
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• pp.371-375
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• 2010

SSD is a storage medium based on NAND Flash memory. Because of its short latency, low power consumption, and resistance to shock, it's not only used in PC but also in server computers. Most SSDs use FTL to overcome the erase-before-overwrite characteristic of NAND flash. There are several types of FTL, but page mapped FTL shows better performance than others. But its usefulness is limited because of its large memory footprint for the mapping table. For example, 64MB memory space is required only for the mapping table for a 64GB MLC SSD. In this paper, we propose a novel caching scheme for the mapping table. By using the mapping-table-meta-data we construct a fully associative cache, and translate the address within O(1) time. The simulation results show more than 80 hit ratio with 32KB cache and 90% with 512KB cache. The overall memory footprint was only 1.9% of 64MB. The time overhead of cache miss was measured lower than 2% for most workload.

• Journal of KIISE:Software and Applications
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• v.35 no.5
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• pp.281-287
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• 2008

Data transfers occur during the execution time of a Java program, from constant to variable, from variable to other variable and so on. Data are located in memory and hence data transfer requires access to memory. As memory access generates both time delay and energy consumption it is absolutely necessary to know the data transfer overheads incurred among different paths not only to write an efficient program but also to build a high-performance Java virtual machine. In this paper we classify Java memory into three different regions, constant, local variable, and field, and then investigate data transfer overheads among these regions. The result says that the transfer between local variables incur the least overhead usually, while the transfer between fields incur the most. The difference of overheads reaches up to a double. Optimization techniques like JIT reduces the data transfer overhead dramatically. It is observed that the overhead is reduced from 14 to 27 times for the case of Hotspot JVM.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.304.1-304.1
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• 2014

Flat-panel displays have been growing as an essential everyday product in the current information/communication ages in the unprecedented speed. The forward-coming applications require light-weightness, higher speed, higher resolution, and lower power consumption, along with the relevant cost. Such specifications demand for a new concept-based materials and applications, unlike Si-based technologies, such as amorphous Si and polycrystalline Si thin film transistors. Since the introduction of the first concept on the oxide-based thin film transistors by Hosono et al., amorphous oxide thin film transistors have been gaining academic/industrial interest, owing to the facile synthesis and reproducible processing despite of a couple of shortcomings. The current work places its main emphasis on the binary oxides composed of ZnO and SnO2. RF sputtering was applied to the fabrication of amorphous oxide thin film devices, in the form of bottom-gated structures involving highly-doped Si wafers as gate materials and thermal oxide (SiO2) as gate dielectrics. The physical/chemical features were characterized using atomic force microscopy for surface morphology, spectroscopic ellipsometry for optical parameters, X-ray diffraction for crystallinity, and X-ray photoelectron spectroscopy for identification of chemical states. The combined characterizations on Zn-Sn-O thin films are discussed in comparison with the device performance based on thin film transistors involving Zn-Sn-O thin films as channel materials, with the aim to optimizing high-performance thin film transistors.

• The KIPS Transactions:PartA
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• v.13A no.5 s.102
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• pp.435-444
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• 2006

Recently, various applications of location trigger service have been required and developed as users of location-based services are increasing. The location trigger is detecting event of entering in, existing in or leaving from pre-specified area, and then alerting by short message service, an e-mall or servicing other pre-defined action to mobile subscribers. The conventional methodology of supporting location trigger is detecting location trigger events as periodical requesting location of mobile communication terminal to location gateway server in mobile communication network. But these conventional methods cause mobile communication interruption when the location trigger services are overloaded; thereby inducing performance of core server to be fell off. So in this paper, we have studied a new location trigger technology, named multilevel location trigger, to reduce mobile core network sewer triggering bottleneck and power consumption caused embedded GPS device of mobile phone. Actually, as design and evaluating the performance of location trigger after building test-bed environment, we contribute toward improving echnology of location trigger.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.654-662
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• 2005

Mobile portable devices for wireless network solely depend on a limited battery power. Therefore, we need to design for wireless communication protocols with an energy efficiency. TCP-Westwood is one of the most important approaches on TCP performance improvement in wireless environments that estimates the available bandwidth by using the sampling mechanism. The advantage is that data can be transmitted efficiently using the estimation of available bandwidth. However, when the sender with TCP-Westwood is in a wireless environment, it does not consider of the sampling mechanism operation. In this thesis, a new energy saving transport protocol, called E2TP(Energy Efficient Transport Protocol), is proposed to solve problems which occur when the sender with TCP-Westwood is in a wireless environment. Also, when there are packet loss while doing frequent link error in a wireless environment, E2TP provides the instantaneous segment size adjustment for a more efficient data retransmission. The simulation result proves that the proposed E2TP has better performance in energy efficiency and throughput than both TCP and TCP-Westwood.

• The KIPS Transactions:PartD
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• v.13D no.7 s.110
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• pp.867-878
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• 2006

In the past few years, the research of sensor networks is forced dramatically. Specially, while the research for maintaining the power of a sensor is focused, we are also concerned nth query processing related with the optimization of multiple continuous queries for decreasing in unnecessary energy consumption of sensor networks. We present the fragmentation algorithm to solve the redundancy problem in multiple continuous queries that increases in the count or the amount of transmitting data in sensor networks. The fragmentation algorithm splits one query into more than two queries using the query index (QR-4ree) in order to reduce the redundant query region between a newly created query and the existing queries. The R*-tree should be reorganized to the QR-tree right to the structure suggested. In the result, we preserve 20 percentage of the total energy in the sensor networks.