• Korean Journal of Optics and Photonics
• /
• v.31 no.1
• /
• pp.7-12
• /
• 2020

In this paper, we experimentally investigate the fiber fuse in single-mode 2-kW-class high-power fiber amplifiers, depending on the cooling method at the splicing point. We measured the temperature of the splicing point between the pump-signal combiner and gain fiber as a function of laser output power. The temperature of the splicing point increased from 20 to 32℃ with a slope of 0.01℃/W, up to 1.2 kW of laser output power. At higher powers the temperature of the splicing point increased dramatically, with a slope of 0.08℃/W. After that, the fiber amplifier was destroyed during operation at 1.96 kW of output power by fiber fuse. The bullet shape, a common feature of fiber fuse, was observed in the damaged passive fiber core of the pump-signal combiner. Later, we adopted an improved water-cooled cold plate to increase the cooling efficiency at the splicing point, and investigated the laser output power. The temperature at the splicing point was 35.8℃ with a temperature-rise slope of 0.007℃/W at the maximum output power of 2.05 kW. The beam quality M² was measured to be less than 1.3, and the output beam's profile was a stable Gaussian shape. Finally, neither fiber fuse nor mode instability was observed in the fiber amplifier at the maximum output power of 2.05 kW.

• Proceedings of the IEEK Conference
• /
• 2000.06a
• /
• pp.53-56
• /
• 2000

In MC-CDMA systems effects of delay spread of the channel are reduced with increased symbol duration by simultaneously transmitting data symbols on the parallel subcarriers. However, the increased symbol duration causes the system to be more vulnerable to time selective fading. In other words, although MC-CDMA systems are robust against frequency selective fading in a multipath environment, they are sensitive to Doppler spread and hence inter-carrier interference is increased. In this paper, we investigate the effects of time selective fading characteristics of the mobile channel from the viewpoint of desired signal power to inter-carrier interference power ratio at the combiner output of the MC-CDMA receiver.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
• /
• 2003.11a
• /
• pp.347-351
• /
• 2003

본 논문에서는 전력 분배비를 변화시킬 수 있는 전력 분배기/합성기를 설계하였다. 전력 분배기/합성기의 ${\lambda}/4$ 전송선로 특성 임피던스를 결합선로 또는 하이브리드로 변환하여 설계하였다. 결합 선로나 하이브리드의 결합포트와 격리포트를 동시에 On/Off시킴으로써 변화하는 임피던스를 이용하여 전력 분배비가 1:1에서 1:0으로 즉 전력이 두개의 포트에 같은 크기로 전달되다가 모든 입력이 하나의 출력포트로 모두 전달되는 전력 분배기를 설계하였다.

• Proceedings of the Korea Institute of Convergence Signal Processing
• /
• 2001.06a
• /
• pp.33-36
• /
• 2001

In MC-CDMA systems effects of delay spread of the channel are reduced with increased symbol duration by simultaneously transmitting data symbols on the parallel subcarriers. However, the increased symbol duration causes the system to be more vulnerable to time selective fading. In this paper, we investigate the effects of time selective fading characteristics of the mobile channel from the viewpoint of desired signal power to inter-carrier interference power ratio at the combiner output of the MC-CDMA receiver.

• Proceedings of the IEEK Conference
• /
• 2000.07b
• /
• pp.1063-1066
• /
• 2000

ln this paper, a new active phase shifter is proposed using a vector sum method, and it is shown that the proposed phase shifter is more efficient than the others in size, power, number of circuits, and gain. Also a unique digital phase control method of the circuit is suggested. The proposed scheme was designed and implemented using a Wilkinson power combiner/divider, a branch line 3dB quadrature hybrid coupler and variable gain amplifiers (VGAs) using dual gate FETs (DGFETs). Furthermore, it is also shown that the proposed scheme is more efficient and works properly with the digital phase control method.

• ETRI Journal
• /
• v.34 no.6
• /
• pp.885-891
• /
• 2012

This paper proposes a high-efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current-mode transformer-based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18-${\mu}m$ RF-CMOS process with a supply voltage of 3.3 V. The measured gain, $P_{1dB}$, and efficiency at $P_{1dB}$ are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25-dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.14 no.11
• /
• pp.1170-1175
• /
• 2003

In this paper, the output power improvement of Push-Push FET DRO by adding the identical DR at the drain port as one used in the gate port, has been theoretically investigated. The investigation shows that the DR located between two microstrip lines locks the phase difference of two FET's outputs at 180 degree and improves the output power of Push-Push FET DRO. Since this effect can be used for correcting the impedance difference between two FETs output circuits and the electrical length error of the power combiner at the output circuit of Push-Push DRO, which may occur when fabricate the oscillator, the oscillator with an additional DR can be useful structure for fabricating oscillator.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.15 no.2
• /
• pp.178-182
• /
• 2004

In this paper, a 90$^{\circ}$ hybrid coupler with both power division and harmonic rejection characteristics is presented by applying a LPF characteristic to a conventional 90$^{\circ}$ hybrid. Since a conventional 90$^{\circ}$ hybrid coupler operates as a power divider/combiner using phase difference, it does not suppress higher order harmonics when it is incorporated with nonlinear amplifier. This requires an additional filter to take into account of the harmonics. The proposed 90$^{\circ}$hybrid coupler power provides the division capability and proper phase difference, as well as harmonic suppression characteristic by integrating LPF characteristic.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.12A
• /
• pp.1019-1024
• /
• 2003

In the thesis, we propose a new type of the predistortion linearizer using frequency multiplier The linearizer utilizing the 2nd and 3th harmonic used the individual control of the 3rd and 5th order intermodulation distortion(IMD) component. This structure is composed of wilkinson power combiner for combine and isolation of output signal, 3rd order IMD product controller using doubler and 5th order IMD product controller using tripler. The proposed predistortion linearizer controlled by individual order is obtained for about -16 dBc and 18 dBc of 3rd order and 5th order IMD components, respectively, over the frequency band 870 MHz to 880 MHz at the output power of 34 dBm/tone.

• 한국정보통신설비학회:학술대회논문집
• /
• 2008.08a
• /
• pp.441-446
• /
• 2008

In this papers, a PLDRO(Phase Locked Dielectric Resonator Oscillator) is designed and implemented at the oscillator in which fundamental frequency is 18.3 GHz. The proposed PLDRO so as to improve the PLDRO of the general structure is designed to the goal of the minimize of the size and the performance improvement. Three VCO(Voltage controlled Oscillator) and the power combiner improved the output power. A VCDRO(Voltage Controlled Dielectric Resonator Oscillator) is manufactured using a varactor diode to tune oscillating frequency electrically, and its phase is locked to reference frequency by SPD(Sampling Phase Detector). This product is fabricated on Teflon substrate with dielectric constant 2.2 and device is ATF -13786 of Ka-band using. This PLDRO generates an output power of 5.67 dBm at 18.3 GHz and has the characteristics of a phase noise of -80.10 dBc/Hz at 1 kHz offset frequency from carrier, the second harmonic suppression of -33 dBc. The proposed PLDRO can be used in Ka-band satellite applications