• ETRI Journal
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• v.42 no.6
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• pp.943-950
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• 2020

We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.

• ETRI Journal
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• v.46 no.2
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• pp.323-332
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• 2024

Receiver and transmitter monolithic microwave integrated circuit (MMIC) multifunction chips (MFCs) for active phased-array antennas for Ka-band satellite communication (SATCOM) terminals have been designed and fabricated using a 0.15-㎛ GaAs pseudomorphic high-electron mobility transistor (pHEMT) process. The MFCs consist of four-channel radio frequency (RF) paths and a 4:1 combiner. Each channel provides several functions such as signal amplification, 6-bit phase shifting, and 5-bit attenuation with a 44-bit serial-to-parallel converter (SPC). RF pads are implemented on the bottom side of the chip to remove the parasitic inductance induced by wire bonding. The area of the fabricated chips is 5.2 mm × 4.2 mm. The receiver chip exhibits a gain of 18 dB and a noise figure of 2.0 dB over a frequency range from 17 GHz to 21 GHz with a low direct current (DC) power of 0.36 W. The transmitter chip provides a gain of 20 dB and a 1-dB gain compression point (P1dB) of 18.4 dBm over a frequency range from 28 GHz to 31 GHz with a low DC power of 0.85 W. The P1dB can be increased to 20.6 dBm at a higher bias of +4.5 V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.12
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• pp.1139-1147
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• 2011

In this paper, a design and fabrication of GaN power amplifier for the S-band frequency (400 MHz bandwidth) are presented. A combining path using ${\lambda}$/4 transmission line is implemented for GaN pallet amp. Both the combiner with suspended-type transmission structure for low-loss and the suspended stripline coupler with aperture coupling for auto gain control are realized for achieving high-power high-efficiency amplifier. Proposed power amplifier demonstrated a 5 kW peak output power, 27.8 % efficiency, 67 dB gain without ALC and a 4 kW peak output power, 25.5 % efficiency, 0.1 dB droop at 200 usec pulse width and 10 % duty with ALC.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.4
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• pp.323-331
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• 1997

In this paper, the high efficiency balanced amplifier is presented as high efficiency power amplifier. This amplifier is basically composed of two FETs, an input power divider, output power combiner, input matching circuits, output matching circuits, second harmonic interconnection circuit and lowpass filter. The second harmonic interconnection circuit is composed of second harmonic frequency bandpass filter and transmission line. This circuit is inserted between the output terminals of the two FEF's output matching circuit, there is a second harmonic standing wave generated between two FET outputs. The electric wall termination is equivalent to the short circuit termination. As a result, the FET output termination condition needed to attain high efficiency is realized. Experimental high efficiency balanced amplifier is constructed to determine its practically attainable efficiency. The input VSWR is 1.27, and the output VSWR is 1.18. Power added efficiency of 75% is attained at 1.75 GHz band about 3W to balanced amplifier.

• Journal of Advanced Navigation Technology
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• v.8 no.2
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• pp.184-190
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• 2004

A feedforward linear power amplifier (FLPA) has been developed for UHF-band RFID reader applications. The main and error amplifiers are composed of a 2 stage so that linearity of the FLPA can be improved. The FLPA has been implemented on an FR-4 substrate (Er=4.7 and thickness=0.8 mm) with 3-dB and 10-dB hybrid couplers for input/output power divider and combiner. For 2-tone measurement (input level=-11 dBm at $f_1$=915 MHz and $f_2$=916 MHz), the FLPA exhibits a -18.52 dBm of $IMD_3$, which indicates that $IMD_3$ cancellation with feedforward loop is more than 27 dB. From 890 to 960 MHz, 1-dB gain compression output power and power gain of the FLPA are higher than 30 dBm and 40 dB, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.43-55
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• 2013

In this paper, we propose a cylindrical active phased array antenna of Beam Steering Characteristics in the horizontal plane(H-plane) and vertical plane(E-Plane) on the cylinder form array structure. We design the bent dipole antenna of the cylindrical array structure adapted excellent mutual-coupling characteristics, designed and manufactured the cylindrical array antennas and power combiner/divider unit for power dividing and combining on the antenna. The radiating elements array spacing of Cylindrical array antenna were determined to avoid grating lobes at half power beam steering. Beam steering of the antenna was implemented with 6-bit phase shifter in the transceiver and have been designed based on the characteristics the antenna beam steering at -24 degrees to 24 degrees horizontal, vertical 0 degrees to 36 degrees beam steering. A cylindrical active phased array antenna that produced for verification the performance of the antenna are measured radiation characteristics in accordance with beam steering at L-Band.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.2
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• pp.262-265
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• 2012

In this paper, a Ka-band 8 W power amplifier module with WR-28 waveguide input and output ports is implemented and measured using four 2 W power amplifier modules and 4:1 waveguide power combiners with high isolation of 25 dB at 35 GHz. The 2 W power amplifier modules are fabricated using waveguide-to-microstrip transitions and show output power of 32.5~33.3 dBm and power gain of 26.9~28.7 dB at 35 GHz. Four 2 W power amplifier modules are combined through 4:1 waveguide power combiners with resistive septum and the combined power shows 39.0 dBm(8 W) under 6 V drain bias and 39.6 dBm(9.1 W) under 6.5 V drain bias at 35 GHz.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.2
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• pp.127-134
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• 2019

With the advancement of IT technology, the amount of data generated has been growing exponentially every year. As an alternative to this, research on distributed systems and in-memory based big data processing schemes has been actively underway. The processing power of traditional big data processing schemes enables big data to be processed as fast as the number of nodes and memory capacity increases. However, the increase in the number of nodes inevitably raises the frequency of failures in a big data infrastructure environment, and infrastructure management points and infrastructure operating costs also increase accordingly. In addition, the increase in memory capacity raises infrastructure costs for a node configuration. Therefore, this paper proposes an in-memory-based hybrid big data processing scheme for improve the big data processing rate. The proposed scheme reduces the number of nodes compared to traditional big data processing schemes based on distributed systems by adding a combiner step to a distributed system processing scheme and applying an in-memory based processing technology at that step. It decreases the big data processing time by approximately 22%. In the future, realistic performance evaluation in a big data infrastructure environment consisting of more nodes will be required for practical verification of the proposed scheme.

• Journal of Communications and Networks
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• v.11 no.1
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• pp.11-19
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• 2009

Multicarrier direct sequence code division multiple access (MC DS-CDMA) is an attractive technique for achieving high data rate transmission. This is valid regardless of whether or not the potentially large peak-to-average power ratio (PAPR) is an important factor for its application. On the other hand, code select CDMA (CS-CDMA) is an attractive technique with constant amplitude transmission of multicode signal regardless of subchannels. This is achieved by introducing a code select method. In this paper, we propose a new multiple access scheme based on the combination of MC DS-CDMA and CS-CDMA. The proposed scheme, which we call MC CS-CDMA, includes as special cases the subclasses of MC DS-CDMA and CS-CDMA. This paper investigates the performance of these systems over a multipath frequency selective fading channel using a RAKE receiver with maximal ratio combiner. In addition, the PAPR of the proposed system is compared with that of both MC DS-CDMA and CS-CDMA. Simulation results demonstrate that the proposed system provides better PAPR reduction than MC DS-CDMA, at the expense of the complexity of the receiver and the number of available users. The numerical result demonstrates that the proposed system has better performance than MC DS-CDMA due to the increased processing gain and time diversity gain.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.9
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• pp.1079-1086
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• 2012

In this paper, X-band 60 W Solid-State Power Amplifier with sequential control circuit and pulse width variation circuit for improve bias of SSPA module was designed. The sequential control circuit operate in regular sequence drain bias switching of GaAs FET. The distortion and efficiency of output signals due to SSPA nonlinear degradation is increased by making operate in regular sequence the drain bias wider than that of RF input signals pulse width if only input signal using pulsed width variation. The GaAs FETs are used for the 60 W SSPA module which is consists of 3-stage modules, pre-amplifier stage, driver-amplifier stage and main-power amplifier stage. The main power amplifier stage is implemented with the power combiner, as a balanced amplifier structure, to obtain the power greater than 60 W. The designed SSPA modules has 50 dB gain, pulse period 1 msec, pulse width 100 us, 10 % duty cycle and 60 watts output power in the frequency range of 9.2~9.6 GHz and it can be applied to solid-state pulse compression radar using pulse SSPA.