• East Asian mathematical journal
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• v.35 no.3
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• pp.285-288
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• 2019

Let $F_n$, $n{\in}{\mathbb{N}}$ be the n - th Fibonacci number, and let (p, q) be one of ordered pairs ($F_{n+2}$, $F_n$) or ($F_{n+1}$, $F_n$). Then we show that the multiplicative inverse of q mod p as well as that of p mod q are again Fibonacci numbers. For proof of our claim we make use of well-known Cassini, Catlan and dOcagne identities. As an application, we determine the number $N_{p,q}$ of nonzero term of a polynomial ${\Delta}_{p,q}(t)=\frac{(t^{pq}-1)(t-1)}{(t^p-1)(t^q-1)}$ through the Carlitz's formula.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.3 s.357
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• pp.61-67
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• 2007

In Reed Solomon decoder, when there are more than 4 error symbols, we usually use Chien search machine to find those error positions. In this case, classical method requires complex and relatively slow digital circuitry to implement it. In this paper we propose New fast and cost effective Chien search machine design method using Galois Subfield transformation. Example is given to show the method is working well. This new design can be applied to the case where there are more than 5 symbol errors in the Reed-Solomon code word.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1495-1507
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• 1993

In this paper, an implementation of RS (Reed-Solomon) code decoder for CDP (Compact Disc Player) using microprogramming method is presented. In this decoding strategy, the equations composed of Newton's identities are used for computing the coefficients of the error locator polynomial and for checking the number of erasures in C2(outer code). Also, in C2 decoding the values of erasures are computed from syndromes and the results of C1(inner code) decoding. We pulled up the error correctability by correcting 4 erasures or less. The decoder contains an arithmetic logic unit over GF(28) for error correcting and a decoding controller with programming ROM, and also microinstructions. Microinstructions are used for an implementation of a decoding algorithm for RS code. As a result, it can be easily modified for upgrade or other applications by changing the programming ROM only. The decoder is implemented by the Logic Level Modeling of Verilog HDL. In the decoder, each microinstruction has 14 bits( = 1 word), and the size of the programming ROM is 360 words. The number of the maximum clock-cycle for decoding both C1 and C2 is 424.