• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.4
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• pp.119-128
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• 2019

Due to the nature of the 3D graphics processor system, many mathematical calculations are required and parallel processing research using GPU (Graphics Processing Unit) is being performed for high-speed processing. In this paper, we propose a 3D graphics processor using MAMS, a parallel processor that does not use cache memory, to solve the GPU problem of increasing bandwidth caused by cache memory miss and the problem that 3D shader processing speed is not constant. The 3D graphics processor using MAMS proposed in this paper designed Vertex shader, Pixel shader, Tiling and Rasterizing structure using DirectX command analysis, the FPGA(Xilinx Virtex6@100MHz) board for MAMS was constructed and designed using Verilog. We compared the processing time of the developed FPGA (100Mhz) and nVidia GeForce GTX 660 (980Mhz), the processing time using GTX 660 was not constant and suing MAMS was constant.

• Journal of the HCI Society of Korea
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• v.2 no.1
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• pp.25-31
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• 2007

We develop an interactive relighting renderer allowing camera view changes based on a deep-frame buffer approach. The renderer first caches the rendering parameters for a given 3D scene in an auxiliary buffer with the same size of the output image. The rendering parameters independent from light changes are selected from the shading models used for shading pixels. Next, as the user interactively edits one light at one time, the relighting renderer instantly re-shades each pixel by updating the contribution of the changed light with the shading parameters cached in the deep-frame buffer. When the camera moves, the cache values should be re-computed because the currently cached values become obsolete. We present a novel method to synthesize them quickly from the cache images of the user specified cameras by using an image-based technique. This computations are all performed on GPU to achieve real-time performance.

• Journal of Korea Game Society
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• v.7 no.3
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• pp.31-38
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• 2007

In this paper, we proposed an effective visibility test architecture with improving the mid-texturing architecture. The proposed architecture uses the property of fragments that the visibility of adjacent fragments is identical, and performs only a single visibility test per fragment. To compare with the mid-texturing architecture, simulation results show that the bandwidth requirements and the cell area of the depth cache in the proposed architecture are reduce by 25% and 34%, respectively, in exchange for less than 5% performance decline.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.145-155
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Fractional Motion Estimation in 8K UHD($7680{\times}4320$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $10{\times}10$ reference data for interpolation, we design 2D cache buffer which consists of the $10{\times}10$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The gate count is 436.5Kgates. The proposed H.264/AVC Fractional Motion Estimation can support 8K UHD at 30 frames per second by running at 187MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.102-111
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD($3840{\times}2160$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $9{\times}9$ reference data for interpolation, we design 2D cache buffer which consists of the $9{\times}9$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.

• Journal of the Korea Computer Graphics Society
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• v.14 no.3
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• pp.31-46
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• 2008

The depth of field is the range that the objects inside of this range treated to be focused. Objects that are placed out of this range are out of focus and become blurred. In computer graphics, generating depth of field effects gives a great reality to rendered images. The previous researches on the depth of field in computer graphics can be divided into two major categories. One of them is the distributed ray tracing that samples the lens area against each pixel. It is possible to obtain precise results without noise if enough number of samples are taken. However, to make a good result, a great number of samples are needed, resulting in an enormous timing requirement. The other approach is the method that approximates depth of field effect by post-processing an image and its depth values computed using a pin-hole camera. Though the second technique is not that physically correct like distributed ray tracing, many approaches which using this idea have been introduced because it is much faster than the first approach. But the post-processing have some limitations because of the lack of ray information. In this paper, we first present an improvement technique that corrects the previous post-processing methods and then propose another one that accelerates the distributed ray tracing by using a radiance caching method.