• 제목/요약/키워드: Pipeline Structure

검색결과 271건 처리시간 0.022초

전기철도와 평행한 매설배관에서 누설전류에 의한 간섭현상의 수치해석적 연구 (Numerical Analysis of the Interference of the Buried Pipeline due to the Stray Current from the Parallel Electric Railway)

  • 정찬웅;최규형
    • 한국가스학회지
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    • 제12권4호
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    • pp.8-13
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    • 2008
  • 전기철도의 궤도 누설전류는 주변 시설물 뿐 만 아니라 궤도 및 부속물의 전식을 일으킬 우려가 있다. 최근에는 누설전류의 영향을 감소시키기 위한 많은 노력이 기울여지고 있다. 본 연구에서는 수치해석 방법을 통하여 궤도와 매설배관의 이격거리, 토양비저항, 배관의 피복저항율, 궤도의 접지저항 등의 요인에 따른 간섭영향을 정량적으로 평가하였다. 이러한 정량적 연구결과를 토대로 주요 변수에 따른 간섭현상의 변화 방향을 예상할 수 있었으며 향후 대책의 수립과 수치해석에 있어서 각 변수의 민감도를 예상할 수 있었다.

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효율적인 웹문서 처리를 위한 HTTP 지연 개선에 관한 연구 (A Study on Improving HTTP latency for the Latency Web Document Processing)

  • 고일석;최우진;나윤지;류승렬
    • 한국콘텐츠학회논문지
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    • 제2권2호
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    • pp.47-52
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    • 2002
  • 인터넷 사용의 증가는 네트워크 부하를 급격히 증가시키고 있으며 이러한 네트워크 부하의 증가는 인터넷 사용자들의 응답속도를 늦추는 요인이 되고 있어 이를 해결하기 위한 각종 연구가 필요하다. P-HTTP는 파이프라인 구조를 통해 HTTP의 성능을 개선한 모델이나 TCP 기반의 동작에서 P-HTTP와 TCP의 상호작용에서 발생하는 문제점으로 인해 성능이 저하된다. 덜 연구에서는 웹문서의 효율적인 처리와 인터넷 응답 속도의 저하를 막기 위해 P-HTTP와 TCP의 상호 작용으로 인해 발생하는 문제점을 분석하고 이를 개선한 모델을 제시하였다. 본 논문에서 제시한 모델은 기존의 파이프라인 방식의 장점과 GETALL 메쏘드가 가지는 장점을 유지하면서 클라이언트 측의 캐시의 효용성을 높일 수 있어 각종 이미지와 멀티미디어 자료를 포함한 웹문서의 처리에서 그 효용성이 있을 것이다.

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A Case Study of Sediment Transport on the Seabed due to Wave and Current Velocities

  • Choi, Byoung-Yeol;Lee, Sang-Gil;Kim, Jin-Kwang;Oh, Jin-Soo
    • Journal of Advanced Research in Ocean Engineering
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    • 제2권3호
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    • pp.99-111
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    • 2016
  • Seabed affected by scouring, sedimentation, and siltation occurrences often cause exposure, which induces risks to existing structures or crude oil or gas pipeline buried subsea. In order to prevent possible risks, more economical structure installation methodology is proposed in this study by predicting and managing the risk. Also, the seabed does not only consist of sandy material, but clayey soil is also widespread, and the effect of undrained shear strength should be considered, and by cyclic environmental load, pore water pressure will occur in the seabed, which reduces shear strength and allows particles to move easily. Based on previous research regarding sedimentation or erosion, the average value of external environmental loads should be applied; for scouring, a 100-year period of environmental conditions should be applied. Also, sedimentation and erosion are mainly categorized by the bed load and suspended load; also, they are calculated as the sum of bed load and suspended load, which can be obtained from the movement of particles caused by sedimentation or erosion.

High-throughput and low-area implementation of orthogonal matching pursuit algorithm for compressive sensing reconstruction

  • Nguyen, Vu Quan;Son, Woo Hyun;Parfieniuk, Marek;Trung, Luong Tran Nhat;Park, Sang Yoon
    • ETRI Journal
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    • 제42권3호
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    • pp.376-387
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    • 2020
  • Massive computation of the reconstruction algorithm for compressive sensing (CS) has been a major concern for its real-time application. In this paper, we propose a novel high-speed architecture for the orthogonal matching pursuit (OMP) algorithm, which is the most frequently used to reconstruct compressively sensed signals. The proposed design offers a very high throughput and includes an innovative pipeline architecture and scheduling algorithm. Least-squares problem solving, which requires a huge amount of computations in the OMP, is implemented by using systolic arrays with four new processing elements. In addition, a distributed-arithmetic-based circuit for matrix multiplication is proposed to counterbalance the area overhead caused by the multi-stage pipelining. The results of logic synthesis show that the proposed design reconstructs signals nearly 19 times faster while occupying an only 1.06 times larger area than the existing designs for N = 256, M = 64, and m = 16, where N is the number of the original samples, M is the length of the measurement vector, and m is the sparsity level of the signal.

SBP를 이용한 해저 천부에 유실된 사석의 조사 (Mapping of the lost riprap in shallow marine sediments using SBP)

  • 신성렬;김찬수;여은민;김영준;하희상
    • 한국마린엔지니어링학회:학술대회논문집
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    • 한국마린엔지니어링학회 2005년도 후기학술대회논문집
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    • pp.220-221
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    • 2005
  • Sub-bottom profiler(SBP) has been used extensively for the mapping of basement in the foundation design of offshore structure, for pre- and post-dredging operations within harbors and channels, for selection of pipeline routes, sitting of drilling platforms, and in the exploration for an aggregates such as sands and gravels. During the construction of Siwha embankment for irrigation water and the expansion of arable land, the breaking of an embankment unfortunately occurred so that a lot of riprap was swept away and widely dispersed by the tide and strong current. The feasibility study for the construction of the tidal-powered electric plant in Siwha embankment was performed quite recently. Therefore we made use of SBP survey to investigate the distribution of the lost riprap. We could successfully map out the distribution of the lost riprap from the reflection amplitude characteristics of the sediments in SBP data set. We demonstrated the variation of reflection amplitude versus the sediments with and/or without riprap by means of the numerical modeling of acoustic wave equation using finite difference method. Also we examined an amplitude anomaly of the ripraped area through the physical modeling using ultrasonic.

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Design of a Fast Multi-Reference Frame Integer Motion Estimator for H.264/AVC

  • Byun, Juwon;Kim, Jaeseok
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제13권5호
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    • pp.430-442
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    • 2013
  • This paper presents a fast multi-reference frame integer motion estimator for H.264/AVC. The proposed system uses the previously proposed fast multi-reference frame algorithm. The previously proposed algorithm executes a full search area motion estimation in reference frames 0 and 1. After that, the search areas of motion estimation in reference frames 2, 3 and 4 are minimized by a linear relationship between the motion vector and the distances from the current frame to the reference frames. For hardware implementation, the modified algorithm optimizes the search area, reduces the overlapping search area and modifies a division equation. Because the search area is reduced, the amount of computation is reduced by 58.7%. In experimental results, the modified algorithm shows an increase of bit-rate in 0.36% when compared with the five reference frame standard. The pipeline structure and the memory controller are also adopted for real-time video encoding. The proposed system is implemented using 0.13 um CMOS technology, and the gate count is 1089K with 6.50 KB of internal SRAM. It can encode a Full HD video ($1920{\times}1080P@30Hz$) in real-time at a 135 MHz clock speed with 5 reference frames.

SVM을 이용한 버터플라이 밸브의 캐비테이션 상태감시 (Cavitation Condition Monitoring of Butterfly Valve Using Support Vector Machine)

  • 황원우;고명환;양보석
    • 한국소음진동공학회논문집
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    • 제14권2호
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    • pp.119-127
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    • 2004
  • Butterfly valves are popularly used in service in the industrial and water works pipeline systems with large diameter because of its lightweight, simple structure and the rapidity of its manipulation. Sometimes cavitation can occur. resulting in noise, vibration and rapid deterioration of the valve trim, and do not allow further operation. Thus, the monitoring of cavitation is of economic interest and is very importance in industry. This paper proposes a condition monitoring scheme using statistical feature evaluation and support vector machine (SVM) to detect the cavitation conditions of butterfly valve which used as a flow control valve at the pumping stations. The stationary features of vibration signals are extracted from statistical moments. The SVMs are trained, and then classify normal and cavitation conditions of control valves. The SVMs with the reorganized feature vectors can distinguish the class of the untrained and untested data. The classification validity of this method is examined by various signals that are acquired from butterfly valves in the pumping stations and compared the classification success rate with those of self-organizing feature map neural network.

RSFQ 4-bit ALU 개발 (Development of an RSFQ 4-bit ALU)

  • 김진영;백승헌;김세훈;정구락;임해용;박종혁;강준희;한택상
    • Progress in Superconductivity
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    • 제6권2호
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    • pp.104-107
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    • 2005
  • We have developed and tested an RSFQ 4-bit Arithmetic Logic Unit (ALU) based on half adder cells and de switches. ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We have simulated the circuit by using Josephson circuit simulation tools in order to reduce the timing problem, and confirmed the correct operation of the designed ALU. We used simulation tools of $XIC^{TM},\;WRspice^{TM}$, and Julia. The fabricated 4-bit ALU circuit had a size of $\3000{\ cal}um{\times}1500{\cal}$, and the chip size was $5{\cal} mm{\times}5{\cal}mm$. The test speeds were 1000 kHz and 5 GHz. For high-speed test, we used an eye-diagram technique. Our 4-bit ALU operated correctly up to 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

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Low-Complexity and Low-Power MIMO Symbol Detector for Mobile Devices with Two TX/RX Antennas

  • Jang, Soohyun;Lee, Seongjoo;Jung, Yunho
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제15권2호
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    • pp.255-266
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    • 2015
  • In this paper, a low-complexity and low-power soft output multiple input multiple output (MIMO) symbol detector is proposed for mobile devices with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing mode and spatial diversity mode in single hardware and shows the optimal maximum likelihood (ML) performance. By applying a multi-stage pipeline structure and using a complex multiplier based on the polar-coordinate, the complexity of the proposed architecture is dramatically decreased. Also, by applying a clock-gating scheme to the internal modules for MIMO modes, the power consumption is also reduced. The proposed symbol detector was designed using a hardware description language (HDL) and implemented using a 65nm CMOS standard cell library. With the proposed architecture, the proposed MIMO detector takes up an area of approximately $0.31mm^2$ with 183K equivalent gates and achieves a 150Mbps throughput. Also, the power estimation results show that the proposed MIMO detector can reduce the power consumption by a maximum of 85% for the various test cases.

A Low-Voltage Low-Power Opamp-Less 8-bit 1-MS/s Pipelined ADC in 90-nm CMOS Technology

  • Abbasizadeh, Hamed;Rikan, Behnam Samadpoor;Lee, Dong-Soo;Hayder, Abbas Syed;Lee, Kang-Yoon
    • IEIE Transactions on Smart Processing and Computing
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    • 제3권6호
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    • pp.416-424
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    • 2014
  • This paper presents an 8-bit pipelined analog-to-digital converter. The supply voltage applied for comparators and other sub-blocks of the ADC were 0.7V and 0.5V, respectively. This low power ADC utilizes the capacitive charge pump technique combined with a source-follower and calibration to resolve the need for the opamp. The differential charge pump technique does not require any common mode feedback circuit. The entire structure of the ADC is based on fully dynamic circuits that enable the design of a very low power ADC. The ADC was designed to operate at 1MS/s in 90nm CMOS process, where simulated results using ADS2011 show the peak SNDR and SFDR of the ADC to be 47.8 dB (7.64 ENOB) and 59 dB respectively. The ADC consumes less than 1mW for all active dynamic and digital circuitries.