• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.12
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• pp.723-731
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• 2005

The $4{\times}4$ homogeneous transformation matrix is a compact representation of orientation and position of an object in robotics and computer graphics. A coordinate transformation is accomplished through the successive multiplications of homogeneous matrices, each of which represents the orientation and position of each corresponding link. Thus, for real time control applications in robotics or animation in computer graphics, the fast multiplication of homogeneous matrices is quite demanding. In this paper, a parallel-architecture vector processor is designed for this purpose. The processor has several key features. For the accuracy of computation for real application, the operands of the processors are floating point numbers based on the IEEE Standard 754. For the parallelism and reduction of hardware redundancy, the processor takes column vectors of homogeneous matrices as multiplication unit. To further improve the throughput, the processor structure and its control is based on a pipe-lined structure. Since the designed processor can be used as a special purpose coprocessor in robotics and computer graphics, additionally to special matrix/matrix or matrix/vector multiplication, several other useful instructions for various transformation algorithms are included for wide application of the new design. The suggested instruction set will serve as standard in future processor design for Robotics and Computer Graphics. The design is verified using FPGA implementation. Also a comparative performance improvement of the proposed design is studied compared to a uni-processor approach for possibilities of its real time application.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1026-1031
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• 2008

Nowdays, homes and small businesses rely more and more PON(Passive Optical Networks) for financial transactions, private communications and even telemedicine. Thus, encryption for these data transactions is very essential due to the multicast nature of the PON In this parer, we presented our implementation of a counter mode AES based on Virtex4 FPGA. Our design exploits three advanced features; 1) Composite field arithmetic SubByte, 2) efficient MixColumn transformation 3) and on-the-fly key-scheduling for fully pipelined architecture. By pipeling the composite field implementation of the S-box, the area cost is reduced to average 17 percent. By designing the on-the-fly key-scheduling, we implemented an efficient key-expander module which is specialized for a pipelined architecture.

• The Journal of the Acoustical Society of Korea
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• v.40 no.6
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• pp.571-577
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• 2021

This study is a study on System On Chip (SOC) that implements virtual engine sound in electric vehicles without engines, and realizes vivid engine sound by combining Adaptive Difference PCM (ADPCM) method and frequency modulation method for satisfaction of driver's needs and safety of pedestrians. In addition, by proposing an electronic sound synthesis algorithm applying Musical Instrument Didital Interface (MIDI), an engine sound synthesis method and a constitutive model of an engine sound generation system are presented. In order to satisfy both drivers and pedestrians, this study uses Controller Area Network (CAN) communication to receive information such as Revolution Per Minute (RPM), vehicle speed, accelerator pedal depressed amount, torque, etc., transmitted according to the driver's driving habits, and then modulates the frequency according to the appropriate preset parameters We implemented an interaction algorithm that accurately reflects the intention of the system and driver by using interpolation for the system, ADPCM algorithm for reducing the amount of information, and MIDI format information for making engine sound easier.