• 제목/요약/키워드: Pin to pin

검색결과 2,304건 처리시간 0.027초

Hidden Indicator Based PIN-Entry Method Using Audio Signals

  • Seo, Hwajeong;Kim, Howon
    • Journal of information and communication convergence engineering
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    • 제15권2호
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    • pp.91-96
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    • 2017
  • PIN-entry interfaces have high risks to leak secret values if the malicious attackers perform shoulder-surfing attacks with advanced monitoring and observation devices. To make the PIN-entry secure, many studies have considered invisible radio channels as a secure medium to deliver private information. However, the methods are also vulnerable if the malicious adversaries find a hint of secret values from user's $na{\ddot{i}}ve$ gestures. In this paper, we revisit the state-of-art radio channel based bimodal PIN-entry method and analyze the information leakage from the previous method by exploiting the sight tracking attacks. The proposed sight tracking attack technique significantly reduces the original password complexities by 93.8% after post-processing. To keep the security level strong, we introduce the advanced bimodal PIN-entry technique. The new technique delivers the secret indicator information through a secure radio channel and the smartphone screen only displays the multiple indicator options without corresponding numbers. Afterwards, the users select the target value by following the circular layout. The method completely hides the password and is secure against the advanced shoulder-surfing attacks.

비정질실리콘 pin태양전지에서 입사광 세기에 따른 전류 저압특성 (Incident Light Intensity Dependences of Current Voltage Characteristics for Amorphous Silicon pin Solar Cells)

  • 장진;박민
    • 대한전자공학회논문지
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    • 제23권2호
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    • pp.236-242
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    • 1986
  • The dependence of the current-voltage characteristics of hydrogenated amorphous silicon pin solar cells on the illumimination light intensity has been investigated. The open circuit voltage increases linearly with increasing the logarithm of light intensity up to AM 1, and nearly saturates above AM 1, indicating the open circuit voltage approaching the built-in potential of the pin solar cell above AM 1. The short circuit current density increase with light intensity in proportion to I**0.85 before and I**0.97 after light exposure. Since the series resistance devreses and shunt resistance increases with light intensily, the fill factor increases with light illumination. To increase the fill factor at high illumination in large area solar cells, t6he grid pattern on the ITO substrates should be made. Long light exposure on the solar cells gives rise to the increase of bulk resistance and defect states, resulting in the decrease of the fil factor and short circuit current density. The potential drop in the bulk of the a-Si:H pin solar cells at short circuit condition increases with decreasing temperature, and increases after long light exposure.

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공정능력을 고려한 체결구 부품의 위치공차 최적화 방법 연구 (A Study on the Optimization of Position Tolerance of Fasteners Considering Process Capability)

  • 이상현;이태근;장성호
    • 대한안전경영과학회:학술대회논문집
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    • 대한안전경영과학회 2008년도 춘계학술대회
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    • pp.417-428
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    • 2008
  • Designers have to consider voice of customer, process capability, manufacturing standards & condition, manufacturing method, characteristics of products to decide tolerances. Especially, in case of position of hole and pin, designers have to consider process capability to decide tolerances. The traditional position tolerances used in a drawing are theoretical values which are allocated to position under the worst case assembling condition that both hole and pin are the maximum material condition(MMC). However, When the process capability is high, more exact product size can be produced under stable manufacturing condition. larger clearance of hole and pin can be allocated. In this point of view, manufacturer could increase the yield by allocating larger position tolerance than theoretical position tolerance of hole and pin considering process capability.

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공정능력을 고려한 체결구 부품의 위치공차 최적화 방법 연구 (A Study on the Optimization of Position Tolerance of Fasteners Considering Process Capability)

  • 이상현;이태근;장성호
    • 대한안전경영과학회지
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    • 제11권1호
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    • pp.75-85
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    • 2009
  • Designers have to consider voice of customer, process capability, manufacturing standards & condition, manufacturing method and characteristics of products to decide tolerances. Especially, in case of position of hole and pin, designers have to consider process capability to decide tolerances. The traditional position tolerances used in a drawing are theoretical values which are allocated to position under the worst case assembling condition that both hole and pin are the maximum material condition(MMC). However, when the process capability is high, more exact product size can be produced under stable manufacturing condition. Larger clearance of hole and pin can be allocated. In this point of view, manufacturer could increase the yield by allocating larger position tolerance than theoretical position tolerance of hole and pin considering process capability.

인공위성용 3차원 메모리 패키징 기술 (3D SDRAM Package Technology for a Satellite)

  • 임재성;김진호;김현주;정진욱;이혁;박미영;채장수
    • 마이크로전자및패키징학회지
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    • 제19권1호
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    • pp.25-32
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    • 2012
  • Package for artificial satellite is to produce mass production for high package with reliability certification as well as develop SDRAM (synchronous dynamic RAM) module which has such as miniaturization, mass storage, and high reliability in space environment. It requires sophisticated technology with chip stacking or package stacking in order to increase up to 4Gbits or more for mass storage with space technology. To make it better, we should secure suitable processes by doing design, manufacture, and debugging. Pin type PCB substrate was then applied to QFP-Pin type 3D memory package fabrication. These results show that the 3D memory package for artificial satellite scheme is a promising candidate for the realization of our own domestic technologies.

사이즈 감소를 위한 이중대역 PIFA 안테나 설계 및 제작 (Design and Fabrication of Dualband PIFA for size reduction)

  • 임동철;박효달
    • 한국통신학회논문지
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    • 제31권9A호
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    • pp.900-905
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    • 2006
  • 본 논문에서는 $2.40{\sim}2.482GHz$$5.75{\sim}5.85GHz$ 대역의 무선 LAN용 PIFA(Planar Inverted F Antenna) 안테나를 설계 제작하였다. 패치의 사이즈 감소를 위해 hair-pin 구조와 short-pin 구조를 갖도록 하였으며, 접지면과 기판사이에 공기층을 삽입하여 VSWR<2.0에서 적절한 대역을 얻고자 하였다. 설계시 주요 파라미터는 hair-pin 길이, 폭, 위치와 공기층의 두께 및 급전위치였으며 최적화된 파라미터를 가지고 실제 제작 및 측정하였다. 제작된 안테나의 측정결과는 다음과 같다. 공진 주파수는 2.37GHz 와 5.86GHz이고, VSWR<2.0에서 각각 약 90MHz 와 350MHz의 대역폭을 얻었으며 $1.91{\sim}4.37dBi$의 이득을 얻었다. 2.4GHz에서 H-평면과 E-평면은 각각 $52.83^{\circ}$$85.90^{\circ}$로 나타났으며 5.8GHz에서 H-평면과 E-평면은 각각 $65.68^{\circ}$$52.143^{\circ}$로 나타났다.

WLAN System을 위한 U-slot 및 Short-pin 결합한 바람개비 모양의 이중대역(5.2/5.8GHz) 마이크로스트립 패치 안테나 설계 및 제작 (Design and Fabrication of a Weathercock-Shaped Double Bandwidth Microstrip Patch Antenna that Combines U-slot and Short-pin for WLAN Systems Systems)

  • 김순섭;최영준;주영달;정용주
    • 한국통신학회논문지
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    • 제38B권5호
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    • pp.337-343
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    • 2013
  • 본 논문에서는 IEEE 802.11 기반의 WLAN(5.2/5.8GHz)대역에서 동작하는 바람개비 모양의 마이크로스트립 패치 안테나를 설계 및 제작하였다. 안테나의 크기는 $17.4{\times}17.4mm^2$이며 FR-4 기판을 사용하였다. 이동성을 위해 소형화하였고, 바람개비 패치 모양에 U-slot 및 Short-pin을 삽입하여 이중대역 공진특성 및 적절한 대역폭을 만족하도록 하였다. 또한 단일 양면기판을 사용하였고, 시뮬레이션설계는 바람개비 모양과 U-slot 및 Short-pin의 위치 변화, 패치길이를 최적화하여 제작 및 측정하였다. 제작한 안테나의 대역폭(Return loss<-10dB)은 5.2~5.8GHz대역에서 695MHz의 대역폭을 얻었다. H면과 E면 방사패턴의 3-dB 빔폭이 각각 $81.13^{\circ}$, $85.43^{\circ}$로 넓은 빔폭을 얻었다. 또한 3.17~4.85dBi의 이득을 얻었다.

엔진 CON-ROD베어링 내 SCUFFING성 향상에 관한 연구 (A study for improvement of engine bearing reliability based on temperature analysis)

  • 최재권;이정현
    • 오토저널
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    • 제14권2호
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    • pp.110-119
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    • 1992
  • Crank pin temperatures were measured and analyzed to find out practical method which can predict the engine bearing reliability. The measuring points were determined to be near the MOFT region and far from that by theoretical calculation. The effect of engine running condition, oil temperature, the change of oil circuit into bearing and crankshaft endplay on crank pin temperature were experimentally tested. The result obtained was as following. The crank pin temperature was dependent on oil film thickness and directly influenced by the change of test condition. Also, the length of the crankshaft endplay was confirmed to be critical to connecting rod bearing failure. In conclusion, we found that the measurement method of crank pin temperature can be used for predicting the engine bearing reliability.

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범용 로직 드라이버를 이용한 880Mbps ATE 핀 드라이버 구현 (Implementation of 880Mbps ATE Pin Driver using General Logic Driver)

  • 최병선;김준성;김종원;장영조
    • 반도체디스플레이기술학회지
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    • 제5권1호
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    • pp.33-38
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    • 2006
  • The ATE driver to test a high speed semiconductor chip is designed by using general logic drivers instead of dedicated pin drivers. We have proposed a structure of general logic drivers using FPCA and assured its correct operation by EDA tool simulation. PCB circuit was implemented and Altera FPGA chip was programmed using DDR I/O library. On the PCB, it is necessary to place two resistors connected output drivers near to the output pin to adjust an impedance matching. We confirmed that the measured results agree with the simulated values within 5% errors at room temperature for the input signals with 800Mbps data transfer rate and 1.8V operating voltage.

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다수 캐비티 금형에서 엘라스토머 수지의 균형충전도 연구 (A Study on the Filling Balance of Elastomer TPVs in Multi-Cavity Injection Mold)

  • 노병수;한성렬;한동엽;정영득
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2006년도 춘계학술대회 논문집
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    • pp.407-408
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    • 2006
  • Almost all injection molds have multi-cavity, which are designed with geometrically balanced runner system in order to made filling balance between cavity to cavity during injection molding. However, filling imbalance has been existed in the geometrically balanced runner system. In this study, we made an experiment and surveyed that are filling balanced variation according to molding condition with thermoplastic vulcanizate (TPV). Also, we conducted experiments in order to know the influence of filling balance for runner core pin (RC pin).

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