• Journal of information and communication convergence engineering
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• v.15 no.2
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• pp.91-96
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• 2017

PIN-entry interfaces have high risks to leak secret values if the malicious attackers perform shoulder-surfing attacks with advanced monitoring and observation devices. To make the PIN-entry secure, many studies have considered invisible radio channels as a secure medium to deliver private information. However, the methods are also vulnerable if the malicious adversaries find a hint of secret values from user's $na{\ddot{i}}ve$ gestures. In this paper, we revisit the state-of-art radio channel based bimodal PIN-entry method and analyze the information leakage from the previous method by exploiting the sight tracking attacks. The proposed sight tracking attack technique significantly reduces the original password complexities by 93.8% after post-processing. To keep the security level strong, we introduce the advanced bimodal PIN-entry technique. The new technique delivers the secret indicator information through a secure radio channel and the smartphone screen only displays the multiple indicator options without corresponding numbers. Afterwards, the users select the target value by following the circular layout. The method completely hides the password and is secure against the advanced shoulder-surfing attacks.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.2
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• pp.236-242
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• 1986

The dependence of the current-voltage characteristics of hydrogenated amorphous silicon pin solar cells on the illumimination light intensity has been investigated. The open circuit voltage increases linearly with increasing the logarithm of light intensity up to AM 1, and nearly saturates above AM 1, indicating the open circuit voltage approaching the built-in potential of the pin solar cell above AM 1. The short circuit current density increase with light intensity in proportion to I**0.85 before and I**0.97 after light exposure. Since the series resistance devreses and shunt resistance increases with light intensily, the fill factor increases with light illumination. To increase the fill factor at high illumination in large area solar cells, t6he grid pattern on the ITO substrates should be made. Long light exposure on the solar cells gives rise to the increase of bulk resistance and defect states, resulting in the decrease of the fil factor and short circuit current density. The potential drop in the bulk of the a-Si:H pin solar cells at short circuit condition increases with decreasing temperature, and increases after long light exposure.

• Proceedings of the Safety Management and Science Conference
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• 2008.04a
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• pp.417-428
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• 2008

Designers have to consider voice of customer, process capability, manufacturing standards & condition, manufacturing method, characteristics of products to decide tolerances. Especially, in case of position of hole and pin, designers have to consider process capability to decide tolerances. The traditional position tolerances used in a drawing are theoretical values which are allocated to position under the worst case assembling condition that both hole and pin are the maximum material condition(MMC). However, When the process capability is high, more exact product size can be produced under stable manufacturing condition. larger clearance of hole and pin can be allocated. In this point of view, manufacturer could increase the yield by allocating larger position tolerance than theoretical position tolerance of hole and pin considering process capability.

• Journal of the Korea Safety Management & Science
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• v.11 no.1
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• pp.75-85
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• 2009

Designers have to consider voice of customer, process capability, manufacturing standards & condition, manufacturing method and characteristics of products to decide tolerances. Especially, in case of position of hole and pin, designers have to consider process capability to decide tolerances. The traditional position tolerances used in a drawing are theoretical values which are allocated to position under the worst case assembling condition that both hole and pin are the maximum material condition(MMC). However, when the process capability is high, more exact product size can be produced under stable manufacturing condition. Larger clearance of hole and pin can be allocated. In this point of view, manufacturer could increase the yield by allocating larger position tolerance than theoretical position tolerance of hole and pin considering process capability.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.25-32
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• 2012

Package for artificial satellite is to produce mass production for high package with reliability certification as well as develop SDRAM (synchronous dynamic RAM) module which has such as miniaturization, mass storage, and high reliability in space environment. It requires sophisticated technology with chip stacking or package stacking in order to increase up to 4Gbits or more for mass storage with space technology. To make it better, we should secure suitable processes by doing design, manufacture, and debugging. Pin type PCB substrate was then applied to QFP-Pin type 3D memory package fabrication. These results show that the 3D memory package for artificial satellite scheme is a promising candidate for the realization of our own domestic technologies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.9A
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• pp.900-905
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• 2006

In this paper, PIFA antenna for $2.40{\sim}2.482GHz\;and\;5.75{\sim}5.85GHz$ is designed, fabricated, and measured. The prototype consist of hair-pin and short-pin. To obtain suitable bandwidth, the form layer is inserted between ground plane and substrate. Important parameters in the design are hair-pin length, width, position, air-gap height, and feed point position. From these parameters optimized, a PIFA antenna is fabricated and measured. The measured results of the antenna are obtained as follows results. The resonant frequency of the fabrication PIFA antenna is 2.37GHz and 5.86GHz bandwidth for approximately 90MHz with 350MHz(VSWR<2.0) and the gain is $1.91{\sim}4.37dBi$. H-plan and E-plan at 2.4GHz and 5.8GHz are shown as $52.83^{\circ},\;85.90^{\circ}\;and\;68.68^{\circ},\;52.143^{\circ}$ respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.5
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• pp.337-343
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• 2013

In this paper, IEEE 802.11 based WLAN(5.2/5.8GHz) wideband Weathercock-shaped microstrip patch antenna was designed and manufactured. The antenna has a size of $17.4{\times}17.4mm^2$ and utilized FR-4 board. The size was minimized for mobility, and Weathercock-shaped U-slot and short-pin was inserted to satisfy adequate bandwidth and double bandwidth resonance characteristics. In addition, the antenna incorporated single both-sided patch, and simulation design optimized the Weathercock-shaped, position of the U-slot and the short-pin, and the length of the patch for the measurement. The manufactured antenna achieved a bandwidth of 695MHz from 5.2~5.8GHz zone(Return loss<-10dB). Achieved a beam width of $81.13^{\circ}$ and $85.43^{\circ}$ for 3-dB beam width of H plane and E p;ane radiation pattern, there was 3.17~4.85dBi gain.

• Journal of the korean Society of Automotive Engineers
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• v.14 no.2
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• pp.110-119
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• 1992

Crank pin temperatures were measured and analyzed to find out practical method which can predict the engine bearing reliability. The measuring points were determined to be near the MOFT region and far from that by theoretical calculation. The effect of engine running condition, oil temperature, the change of oil circuit into bearing and crankshaft endplay on crank pin temperature were experimentally tested. The result obtained was as following. The crank pin temperature was dependent on oil film thickness and directly influenced by the change of test condition. Also, the length of the crankshaft endplay was confirmed to be critical to connecting rod bearing failure. In conclusion, we found that the measurement method of crank pin temperature can be used for predicting the engine bearing reliability.

• Journal of the Semiconductor & Display Technology
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• v.5 no.1 s.14
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• pp.33-38
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• 2006

The ATE driver to test a high speed semiconductor chip is designed by using general logic drivers instead of dedicated pin drivers. We have proposed a structure of general logic drivers using FPCA and assured its correct operation by EDA tool simulation. PCB circuit was implemented and Altera FPGA chip was programmed using DDR I/O library. On the PCB, it is necessary to place two resistors connected output drivers near to the output pin to adjust an impedance matching. We confirmed that the measured results agree with the simulated values within 5% errors at room temperature for the input signals with 800Mbps data transfer rate and 1.8V operating voltage.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.407-408
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• 2006

Almost all injection molds have multi-cavity, which are designed with geometrically balanced runner system in order to made filling balance between cavity to cavity during injection molding. However, filling imbalance has been existed in the geometrically balanced runner system. In this study, we made an experiment and surveyed that are filling balanced variation according to molding condition with thermoplastic vulcanizate (TPV). Also, we conducted experiments in order to know the influence of filling balance for runner core pin (RC pin).