• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1498-1499
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• 1998

Thin film inductors of 10 mm ${\times}$ 10 mm with spiral pattern of 14 turns were fabricated by sputtering, photo-masking, and etching processes. Their impedence characteristics and annealing after effects were investigated. After magnetic annealing, the impedence characteristics of the inductors were improved at comparatively low frequencies, but the tendencies of it for thr frequency changes were almost same. These improvement was caused by the annihilation of the internal stresses of films, Uniaxial field annealed thin film inductor had an inductance of 1000 nH, resistance of 6 $\Omega$, and quality factor of 1 at 2 MHz.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.194.1-194.1
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• 2014

기저면에 구조적 결함을 도입함으로써 그래핀과 $MoS_2$와 같은 이차원 결정의 물리, 화학, 전기 및 기계적 성질을 제어하려는 연구가 폭넓게 수행되고 있다. 본 연구에서는 플라즈마 속의 산소 래디컬을 이용하여 기계적 박리법으로 만들어진 단일층 그래핀과 $MoS_2$ 표면에 구조적 결함을 유도하고 제어하는 방법을 개발하였다. 라만 및 광발광 분광법을 통해 생성된 결함 밀도를 측정하고 전하 밀도 등의 화학적 변화를 추적하였다. 그래핀의 경우 산소 플라즈마 처리 시간에 따라 결함(defect)의 정도를 보여주는 라만 D-봉우리의 높이와 넓이가 커짐을 확인하였고 이를 G-봉우리의 높이와 비교하여 정량하였다. $MoS_2$의 경우 $E{^1}_{2g}$와 $A_{1g}$-봉우리의 높이가 점점 감소하고 광발광의 세기 또한 감소함을 확인하였다. 또한 본 연구에서는 기판의 편평도가 결함 생성 속도에 미치는 영향을 비교 및 분석하여 반응 메커니즘을 제시하고자 한다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2015.11a
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• pp.332-332
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• 2015

Block Copolymer lithography는 deep nano-scale device 제작을 위한 기존의 top-down방식의 photo-lithography를 대체할만한 기술로 많은 연구가 진행되고 있다. polystyrene(PS)/poly-methyl methacrylate (PMMA)로 구성된 BCP의 nano-scale PS mask는 일반적인 플라즈마 공정에 쉽게 damage를 입는다. 중성빔 식각을 이용하여 식각 공정 중 발생하는 BCP의 degradation을 감소시키고, 비등방성 식각 profile을 얻을 수 있으며 sidewall roughness(SWR)와 sidewall angle(SWA)가 향상되는 것을 알 수 있었다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.11a
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• pp.141-141
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• 2012

고종횡비 10:1 비아를 Si wafer 상에 형성하기 위해 $7{\mu}m$ 직경의 마스크로 포토작업하여 Cr층을 100nm 스퍼터링하여 PR(photo resistor) 대신의 에칭 barrier 막으로 사용하였다. 얼라인, 노광, 현상을 거쳐 Cr에칭, PR 제거후 ICP(inductively coupled plasma) 공정으로 Si deep etching하여 via 직경 $10.16{\mu}m$, 깊이 $102.5{\mu}m$의 고종횡비 비아를 형성하였다. 구리필링도금을 위해서 필수적인 seed layer는 단층 또는 다층의 금속막을 스퍼터링 법으로 형성하였다. 형성된 seed layer 단면을 FE-SEM(Field emission scanning electron microscope)으로 관찰하여 내부에 seed 층의 형성 유무를 확인하였다.

• Electrical & Electronic Materials
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• v.10 no.10
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• pp.1034-1040
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• 1997

A solar cell conversion effiency was degraded by grain boundary effect in polycrystalline silicon. Grain boundaries acted as potential barriers as well as recombination centers for the photo-generated carriers. To reduce these effects of the grain boundaries we investigated various influencing factors such as emitter thickness thermal treatment preferential chemical etching of grain boundaries grid design contact metal and top metallization along boundaries. Pretreatment in $N_2$atmosphere and gettering by POCl$_3$and Al were performed to obtain multicrystalline silicon of the reduced defect density. Structural electrical and optical properties of slar cells were characterized before and after each fabrication process. Improved conversion efficiencies of solar cell were obtained by a combination of pretreatment above 90$0^{\circ}C$ emitter layer of 0.43${\mu}{\textrm}{m}$ Al diffusion in to grain boundaries on rear side fine grid finger top Yb metal and buried contact metallization along grain boundaries.

• Journal of the Semiconductor & Display Technology
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• v.16 no.1
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• pp.65-69
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• 2017

This paper presents a Technology-CAD (TCAD) simulation of the characteristics of crystalline Si pillar array solar cells. The junction depth and the surface concentration of the solar cells were optimized to obtain the targeted sheet resistance of the emitter region. The diffusion model was determined by calibrating the emitter doping profile of the microscale silicon pillars. The dimension parameters determining the pillar shape, such as width, height, and spacing were varied within a simulation window from ${\sim}2{\mu}m$ to $5{\mu}m$. The simulation showed that increasing pillar width (or diameter) and spacing resulted in the decrease of current density due to surface area loss, light trapping loss, and high reflectance. Although increasing pillar height might improve the chances of light trapping, the recombination loss due to the increase in the carrier's transfer length canceled out the positive effect to the photo-generation component of the current. The silicon pillars were experimentally formed by photoresist patterning and electroless etching. The laboratory results of a fabricated Si pillar solar cell showed the efficiency and the fill factor to be close to the simulation results.

• Proceedings of the KSME Conference
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• 2004.04a
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• pp.1364-1369
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• 2004

New method for the design, fabrication, and calibration of micro-machined heat flux sensor has been developed. Two types of micro-machined heat flux sensor having different thicknesses of the thermal-resistance layer are fabricated using the MEMS technique. Photo-resist patterning using a chrome mask, bulk-etching and copper-nickel sputtering using a shadow mask are applied to make heat flux sensors, which are calibrated in the convection-type heat flux calibration facility. The sensitivity of the device varies with thermal-resistance layer, and hence can be used to measure the heat flux in heat-transfer phenomena.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.333-338
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• 1999

Thin film inductors of $10 mm \times 10 mm$ with inner coil type of 14 turns were fabricated by sputtering, photo-masking, and etching processes. Their characteristics of impedances and annealing after were investigated. The properties of impedances of the thin film magnetic core inductors with inner coil type were improved by magnetic field annealing due to the removal of residual stress and the improvement magnetic properties of magnetic films. But the characteristics of frequency of the thin film magnetic core inductors were not improved by magnetic field annealing due to properties of the spiral pattern and inner coil type. The thin film magnetic core inductor annealed by uniaxal field annealing method showed an inductance of 1000 nH and resistance of$ 6 \Omega$ of 1 at 2 MHz.

• Journal of the Korean Society of Mechanical Technology
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• v.13 no.4
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• pp.93-99
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• 2011

This paper presents a new type of optical silicon accelerometer using deep reactive ion etching (DRIE) and micro-stereolithography technology. Optical silicon accelerometer is based on a mass suspended by four vertical beams. A vertical shutter at the end of the mass can only moves along the sensing axis in the optical path between two single-mode optical fibers. The shutter modulates intensity of light from a laser diode reaching a photo detector. With the DRIE technique for (100) silicon, it is possible to etch a vertical shutter and beam. This ensures low sensitivity to accelerations that are not along the sensing axis. The microstructure for sensor packaging and optical fiber fixing was fabricated using micro stereolithography technology. Designed sensors are two types and each resonant frequency is about 15 kHz and 5 kHz.

• Journal of Industrial Technology
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• v.43 no.1
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• pp.49-55
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• 2023

Cluster tools are extensively employed in various wafer fabrication processes within the semiconductor manufacturing industry, including photo lithography, etching, and chemical vapor deposition. Contemporary fabrication facilities encounter customer orders with technical specifications that are similar yet slightly varied. Consequently, modern fabrications concurrently manufacture two or three different wafer types using a cluster tool to maximize chamber utilization and streamline the flow of wafer lots between different process stages. In this review, we introduce two methods of concurrent processing of multiple wafer types: 1) concurrent processing of multiple wafer types with different job flows, 2) concurrent processing of multiple wafer types with identical job flows. We describe relevant research trends and achievements and discuss future research directions.