• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.424-424
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• 2009

그라핀은 밴드갭이 없어서 세미메탈의 성질을 띠므로 초고속 RF 소자에는 응용이 가능하지만, 현재 사용되는 반도체 칩에 사용하기가 불가능하다. 그러나 그라핀을 매우 좁은 리본 형태로 만들 경우 밴드갭이 생기고 이에 따라 반도체특성을 뛰게 된다. 이러한 특성은 시뮬레이션을 통해서만 이해되다가 2007년 P. Kim이 그라핀 나노리본의 밴드캡이 리본의 폭이 좁아짐에 따라 증가함을 실험적으로 최초로 발표하였다. 하지만 그라핀을 나노리본형태로 식각 방법에 대해서는 정확히 연구되지 않았다. 따라서 본 연구에서는 $O_2$ plasma ashing 방법을 이용하여 그라핀을 식각하는 방법에 대해 연구하였다. 먼저 Si기판을 initial cleaning 한 후, highly-oriented pyrolytic graphite(HOPG)를 이용하여 기존의 mechanical exfoliation 방식을 통해 그라핀을 형성하였다. Photo-lithography 방법을 통하여 패터닝한 후, 그라핀을 식각하기 위하여 Reactive Ion Etcher (RIE) system을 이용한 $O_2$ plasma ashing을 50 W에서 1 분간 실시하였다. 다시 image reverse photo-lithography 과정과 E-beam evaporator system를 통해서 Al 전극을 형성하여 graphene-FET를 제작하였고, 광학 현미경과 AFM (Atomic force microscope)을 통해 두께를 확인하였다. 본 연구를 통하여 $O_2$ plasma ashing을 이용하여 쉽게 그라 E을 식각할 수 있음을 확인 하였으며, 제작된 소자의 전기적 특성에 대해서 현재 실험중에 있다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.26.1-26.1
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• 2011

We investigated the atomic layer deposition (ALD) process for nitrogen doped ZnO and the application for n-ZnO : N/p-Si (NW) coaxial hetero-junction photodetectors. ALD ZnO:N was deposited using diethylzinc (DEZ) and diluted $NH_4OH$ at $150^{\circ}C$ of substrate temperature. About 100~300 nm diameter and 5 um length of Si nanowires array were prepared using electroless etching technique in 0.108 g of $AgNO_3$ melted 20 ml HF liquid at $75^{\circ}C$. TEM images showed ZnO were deposited on densely packed SiNW structure achieving extraordinary conformality. When UV (360 nm) light was illuminated on n-ZnO:N/p-SiNW, I-V curve showed about three times larger photocurrent generation than film structure at 10 V reverse bias. Especially, at 660 nm wave length, the coaxial structure has 90.8% of external quantum efficiency (EQE) and 0.573 A/W of responsivity.

• Transactions of Materials Processing
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• v.18 no.4
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• pp.310-316
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• 2009

Micro lens array(MLA) is widely used in information technology(IT) industry fields for various applications such as a projection display, an optical power regulator, a micro mass spectrometer and for medical appliances. Recently, MLA have been fabricated and developed by using a reflow method having the processes of micro etching, electroplating, micro machining and laser local heating. Laser thermal relaxation method is introduced in marking of microdots on the surface of densified glass. In this paper, we have proposed a new direct fabrication process using UV laser local thermal-expansion(UV-LLTE) and investigated the optimal processing conditions of MLA on the surface of negative photo-resist material. We have also studied the 3D shape of the micro lens obtained by UV laser irradiation and the optimal process conditions. And then, we made chrome mold by electroplating. After that, we made MLA using chrome mold by hot embossing processing. Finally, we have measured the opto-physical properties of micro lens and then have also tested the possibility of MLA applications.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.15-22
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• 1999

Generally, many equipments and a long lead time ale required to manufacture the build-up multilayer board through various processes such as etching, plating, drilling etc. Wet process is suitable for mass production, however it is not adequate for manufacturing prototype in developing stage. In this study, a silk screen printing technology is introduced to make a prototype build-up multilayer board. As for the material photo/thermal curable resin and conductive paste are used for forming dielectric and conductor. And conductive paste fills vias for interconnecting each layer, and also is used for circuit patterning by silk screen technology. Finally, the basic concept and the possibility of build-up multilayer board prototype is proposed and verified as a powerful approach, compared with the conventional processes.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.84-84
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• 2010

In this study, we report on the novel lithographic patterning method to fabricate organic-semiconductor devices based on photo and e-beam lithography with well-known silicon technology. The method is applied to fabricate pentacene-based organic field effect transistors. Owing to their solubility, sub-micron sized patterning of P3HT and PEDOT has been well established via micromolding in capillaries (MIMIC) and inkjet printing techniques. Since the thermally deposited pentacene cannot be dissolved in solvents, other approach was done to fabricate pentacene FETs with a very short channel length (~30nm), or in-plane orientation of pentacene molecules by using nanometer-scale periodic groove patterns as an alignment layer for high-performance pentacene devices. Here, we introduce the atomic layer deposition of $Al_2O_3$ film on pentacene as a passivation layer. $Al_2O_3$ passivation layer on OTFTs has some advantages in preventing the penetration of water and oxygen and obtaining the long-term stability of electrical properties. AZ5214 and ma N-2402 were used as a photo and e-beam resist, respectively. A few micrometer sized lithography patterns were transferred by wet and dry etching processes. Finally, we fabricated sub-micron sized pentacene FETs and measured their electrical characteristics.

• Current Optics and Photonics
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• v.5 no.3
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• pp.243-249
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• 2021

In this paper, the sensing characteristics of a double cladding fiber (DCF) long-period fiber grating (LPFG) to the surrounding refractive index (SRI) are studied. The outer cladding of the DCF plays the role of the overlay, thus, the mode transition (MT) phenomenon of DCF can be induced by etching the outer cladding radius instead of coating overlays. The response characteristics of the effective refractive index (ERI) of the cladding mode to the outer cladding radius are analyzed. It is found that in the MT range, the change rate of ERIs of cladding modes is relatively larger than that for other ranges. Further, based on the features of the mode transition region (MTR), the phase-matching curve of the 11^th cladding mode is investigated, and the response of the DCF-LPFG to the SRI is characterized by the change of wavelength intervals between the dual peaks under different outer cladding radii. The numerical simulation results show that the SRI sensitivity is greatly improved, which is available to 3484.0 nm/RIU with the fitting degree 0.998 in the SRI range of 1.33-1.37. The proposed DCF-LPFG can provide new theoretical support for designing the DCF-LPFG refractive index sensor with excellent performances of sensitivity, linearity and structure.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.189-189
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• 2015

Plasmonics, sensor, field effect transistors, solar cells 등 다양한 적용분야를 가지는 실리콘 구조체는 제작공정에 의해 전기적 및 광학적 특성이 달라지기 때문에 적합한 나노구조 제작방법이 요구되고 있다. 나노구조체 제작방법으로는 Photo lithography, Extreme ultraviolet lithography (EUV), Nano imprinting lithography (NIL), Block copolymer (BCP) 방식의 방법들이 연구되고 있으며, 특히 BCP는 direct self-assembly 특성을 가지고 있으며 가격적인 면에서도 큰 장점을 가진다. 하지만 BCP를 mask로 사용하여 식각공정을 진행할 경우 BCP가 버티지 못하고 변형되어 mask로서의 역할을 하지 못한다. 이러한 문제를 해결하기 위하여 본 논문에서는 BCP와 질화막을 이용한 double mask 방법을 사용하였다. 기판 위에 BCP를 self-assembly 시키고 mask로 사용하여 hole 부분으로 노출된 기판을 Ion gun을 통해 질화 시킨 후에 BCP를 제거한다. 기판 위에 hole 모양의 질화막 표면은 BCP와 다르게 etching 공정 중 변형되지 않는다. 이러한 질화막 표면을 mask로 사용하여 pillar pattern의 실리콘 나노구조체를 제작하였다. 질화막 mask로 사용되는 template은 PS와 PMMA로 구성된 BCP를 사용하였다. 140kg/mol의 polystyrene과 65kg/mol의 PMMA를 톨루엔으로 용해시키고 실리콘 표면 위에 spin coating으로 도포하였다. Spin coat 후 230도에서 40시간 동안 열처리를 진행하여 40nm의 직경을 가진 PS-b-PMMA self-assembled hole morphology를 형성하였다. 질화막 형성 및 etching을 위한 장비로 low-energy Ion beam system을 사용하였다. Reactive Ion beam은 ICP와 3-grid system으로 구성된 Ion gun으로부터 형성된다. Ion gun에 13.56 MHz의 frequency를 갖는 200W 전력을 인가하였다. Plasma로부터 나오는 Ion은 $2{\Phi}$의 직경의 hole을 가지는 3-grid hole로 추출된다. 10~70 voltage 범위의 전위를 plasma source 바로 아래의 1st gird에 인가하고, 플럭스 조절을 위해 -150V의 전위를 2nd grid에 인가한다. 그리고 3rd grid는 접지를 시켰다. chamber내의 질화 및 식각가스 공급은 2mTorr로 유지시켰다. 그리고 기판의 온도는 냉각칠러를 이용하여 -20도로 냉각을 진행하였다. 이와 같은 공정 결과로 100 nm 이상의 높이를 갖는 40 nm직경의 균일한 Silicon pillar pattern을 형성 할 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.658-658
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• 2013

Graphene is an attractive material for various device applications due to great electrical properties and chemical properties. However, lack of band gap is significant hurdle of graphene for future electrical device applications. In the past few years, several methods have been attempted to open and tune a band gap of graphene. For example, researchers try to fabricate graphene nanoribbon (GNR) using various templates or unzip the carbon nanotubes itself. However, these methods generate small driving currents or transconductances because of the large amount of scattering source at edge of GNRs. At 2009, Bai et al. introduced graphene nanomesh (GNM) structures which can open the band gap of large area graphene at room temperature with high current. However, this method is complex and only small area is possible. For practical applications, it needs more simple and large scale process. Herein, we introduce a photosensitive graphene device fabrication using CdSe QD coated nano-porous graphene (NPG). In our experiment, NPG was fabricated by thin film anodic aluminum oxide (AAO) film as an etching mask. First of all, we transfer the AAO on the graphene. And then, we etch the graphene using O2 reactive ion etching (RIE). Finally, we fabricate graphene device thorough photolithography process. We can control the length of NPG neckwidth from AAO pore widening time and RIE etching time. And we can increase size of NPG as large as 2 $cm^2$. Thin CdSe QD layer was deposited by spin coatingprocess. We carried out NPG structure by using field emission scanning electron microscopy (FE-SEM). And device measurements were done by Keithley 4200 SCS with 532 nm laser beam (5 mW) irradiation.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.254-254
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• 2011

The memories with nano-particles are very attractive because they are promising candidates for low operating voltage, long retention time and fast program/erase speed. In recent, various nano-floating gate memories with metal-oxide nanocrystals embedded in organic and inorganic layers have been reported. Because of the carrier generation in semiconductor, induced photon pulse enhanced the program/erase speed of memory device. We studied photo-induced electrical properties of these metal-oxide nanocrystal memory devices. At first, 2~10-nm-thick Sn and In metals were deposited by using thermal evaporation onto Si wafer including a channel with $n^+$ poly-Si source/drain in which the length and width are 10 ${\mu}m$ each. Then, a poly-amic-acid (PAA) was spin coated on the deposited Sn film. The PAA precursor used in this study was prepared by dissolving biphenyl-tetracarboxylic dianhydride-phenylene diamine (BPDA-PDA) commercial polyamic acid in N-methyl-2-pyrrolidon (NMP). Then the samples were cured at 400$^{\circ}C$ for 1 hour in N atmosphere after drying at 135$^{\circ}C$ for 30 min through rapid thermal annealing. The deposition of aluminum layer with thickness of 200 nm was followed by using a thermal evaporator, and then the gate electrode was defined by photolithography and etching. The electrical properties were measured at room temperature using an HP4156a precision semiconductor parameter analyzer and an Agilent 81101A pulse generator. Also, the optical pulse for the study on photo-induced electrical properties was applied by Xeon lamp light source and a monochromator system.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.05a
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• pp.956-959
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• 2002

In this work, a new non-lithographic micro-fabrication technique is presented. The motivation of this work is to overcome the demerits of the most commonly used photo-lithographic techniques. The micro-fabrication technique presented in this work is a two-step process which consists of mechanical scribing followed by chemical etching. This method has many advantages over other micro-fabrication techniques since it is simple, cost-effective, rapid, and flexible. Also, the technique can be used to obtain a metal structure which has sub-micrometer width patterns. In this paper, the concept of this method and its application to microsystem technology are described.