• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.89-96
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• 1995

Lateral p-i-n photodiodes have been fabricated, electrically tested, and incorporated into microwave control circuits such as an optically excited microwave atttenuator and reflection type phase shifter. Circuit design procedures for the loaded-line phase shifter with the optically controlled p-i-n photodiode are presented. The equal loss loading mode presented for the first time for the phase shifter circuits with lossy load allows an equal insertion loss of the phase shifter in both of its phase states. It is found that the insertion loss of the equal loss loading mode phase shifter constructed with the fabricated p-i-n photodiode load are about 3dB for 11.25$^{\circ}$ bit and 1dB for 5.625$^{\circ}$ bit for the frequency range of 2GHz to 11GHz.

• Journal of Advanced Navigation Technology
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• v.18 no.4
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• pp.341-346
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• 2014

This paper has presented the design and fabrication of phase correlator for wideband digital frequency discriminator (DFD) operating over the 6.0 to 18.0 GHz frequency range. Fabricated DFD phase correlator has been measured I or Q output signal, and analyzed frequency discrimination error. The operation of the proposed mixer type correlator has been analyzed by deriving some analytic equations. To design the phase correlator, this paper has modeled and simulated IQ mixer and 8-way power divider by using RF simulation tool. Designed phase correlator has fabricated and measured. The phase error and frequency discrimination error have been presented using by measured I and Q output signal. Over the 6.0~18.0 GHz range, the root mean square(RMS) phase error is $4.81^{\circ}$, RMS and frequency discrimination error is 1.49 MHz, RMS.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.96-102
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• 2014

In this paper, we proposed new dual-rail data encoding that mixed 4-phase handshaking protocol and 2-phase handshaking protocol for asynchronous system design to reduce signal activities and power consumption. The dual-rail data encoding 4-phase handshaking protocol should leat to much signal activities and power consumption by return to space state. Ideally, the dual-rail data encoding 2-phase handshaking protocol should lead to faster circuits and lower power consumption than the dual-rail 4-phase handshaking protocol, but can not designed using standard library. We use a benchmark circuit that contains a multiplier block, an adder block, and latches to evaluate the proposed dual-rail data encoding. The benchmark circuit using the proposed dual-rail data encoding shows an over 35% reduction in power consumption with 4-phase dual-rail data encoding.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.311-317
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• 2004

A low loss reflection type analog phase shifter which is realized with two varactors and branch coupler. is described. A new design technique for the large phase shift is applied using short stub microstripe lines. This paper presented the realization of design and experimental results. Through the experiment using the duroid microstrip line and varactors, the phase of 2.26GHz signal is controlled to the DC voltage with the phase shift range of 170$^{\circ}$. The achieved insertion loss of less than 3㏈ and the return loss of mote than 12㏈ are achieved over all phase states.

• Journal of Korean Society for Quality Management
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• v.39 no.2
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• pp.329-336
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• 2011

The purpose of Phase I clinical trial is to identify the maximum tolerated dose with specific toxicity rate. The standard TER design does not guarantee the pre-specified toxicity rate. It depends on the dose-toxicity curves. Therefore it is necessary to check the expected toxicity rate of various dose-toxicity curves before we conduct clinical trials. We developed TERAplusB library to help this situation, especially in cancer research. This package will help design the cancer clinical trial. We can compare the expected toxicity rates, the expected number of patients, and the expected times calculated with various dose-toxicity curves. This process will help find the best clinical trial design of the proposed drug.

• Proceedings of the Korean Institute Of Construction Engineering and Management
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• 2007.11a
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• pp.797-800
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• 2007

Value Engineering(VE) is being applied as an useful tool to eliminate the waste of cost and noneffective factors previously in construction projects. Ministry of construction and transportation' has been accordingly enforcing extensionally design phase VE to the construction costing more than 10 billion won, an importance of design phase VE. Although there are legal supports and technical effects, an effect about an introduction of design phase VE can not be applied properly because of several problems at the process. So, in this study, try to find out competency factors of design phase VE to enforce a competency of VE team as a basic database for developing a check list, and estimate weight. For the result, find out a competency evaluation item and organize as a team knowledge, a team work skill and a team attitude. Perform a first survey to verify a reliability and propriety regarding the found competency evaluation, perform the second survey competency as to evaluation item of the found 1, 2, 3 class and then estimate the weight by AHP.

• Journal of the Korean Institute of Rural Architecture
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• v.5 no.3
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• pp.34-43
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• 2003

This study attempts to understanding of outer space elements in a rural house through an analysis nouns for function definition phase in design value engineering. To choose main check objects, this study examines requests by rural dwellers and analyze function definition in design value engineering. The rural dwellers prefers that barrier free design, outdoor working space and security of calamity. Each selected elements are classified the nouns into a main noun by analysis function definition nouns at design VE phase. The nouns are reclassified into the main nouns as a distance, a space, and a form.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.21-24
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• 2000

This paper introduces the design and implementation of a Ku-band 5-bit monolithic phase shifter with a ceramic package. The 5-bit phase shifter MMIC was designed and fabricated by using GaAs MESFET switches. The packaged phase shifter demonstrates a phase error less than 11.3 $^{\circ}$ RMS and an insertion loss variation less than 1.0㏈ RMS for 13∼15㎓. For all 32 states, an insertion loss is measured to be 12.2${\pm}$2.2㏈, an input return loss more than 5.0㏈, and an output return loss more than 6.2㏈ from 13㎓ to 15㎓. The chip size of the 5-bit phase shifter MMIC is 2.35${\times}$1.65mm$\^$2/ including digital control circuits. The size of the ceramic packaged phase shifter is 7.2${\times}$6.2mm$\^$2/.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.370-374
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• 2002

This paper describes the design and fabrication of distributed analog phase shifter circuit. The phase shifter consist of coplanar waveguide(CPW) lines that are periodically loaded with voltage tunable (Ba,Sr)TiO$_3$ thin film interdigital(IDT) capacitors deposited by the pulsed laser deposition(PLD) on (001) MgO single crystals. The phase velocity on these IDT loaded CPW lines is a function of applied bias voltage, thus resulting in analog phase shifting circuits. The measured differential phase shift is 48$^{\circ}$ and the insertion loss decreases from -5㏈ to -3㏈ with increasing bias voltage from 0 to 40 V at 100㎐.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1396-1406
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• 2016

A novel controller design is presented for the recently proposed electric springs (ESs). The dynamic modeling is analyzed first, and the initial Bode diagram is derived from the s-domain transfer function in the open loop. The design objective is set according to the characteristics of a minimum phase system. Step-by-step optimizations of the Bode diagram are provided to illustrate the proposed controller, the design of which is different from the classical multistage leading/lagging design. The final controller is the accumulation of the transfer function at each step. With the controller and the recently proposed δ control, the critical load voltage can be regulated to follow the desired waveform precisely while the fluctuations and distortions of the input voltage are passed to the non-critical loads. Frequency responses at any point can be modified in the Bode diagram. The results of the modeling and controller design are validated via simulations. Hardware and software designs are provided. A digital phase locked loop is realized with the platform of a digital signal processor. The effectiveness of the proposed control is also validated by experimental results.