• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.4
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• pp.298-308
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• 2017

This paper presents a Interleaved Buck Converter(IBC) system with Random PWM to reduce electromagnetic noise by harmonics. Swithced mode power supply generally controlled by high switching frequency have a electromagnetic interference(EMI) issue due to the high-voltage/high-current switching to regulate the voltage in buck converter. To solve the problem. we present a novel IBC system with PRBS. IBC system has two active switches with 180 phase difference that controll the cicuit with two PWM signal. IBC system may be disadventageous for the cost due to the addtion of one set of switch, but it has adventages of power distribution, current ripple cancellation, fast transient response, and passive component size reduction. To verify the validity of study, simulation program has been bulit using PSIM and the experimental results of IBC system using RPWM was compared with the conventinal PWM and randomized PWM.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.