• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.2
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• pp.145-151
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• 2008

This paper proposes the PLL method using positive sequence voltage which is estimated by full-order state observer to find an accurate phase angle under the condition of unbalanced utility voltage. The proposed method uses the full-order state observer instead of existing method(APF All Pass Filter) to find a positive sequence of a utility voltage and this proposed method improves transient response of an estimated phase angle when a three-phase utility voltage becomes unbalanced. To compare proposed method withexisting method, experiments have been done for a phase angle detection of utility voltage when a three-phase utility voltage becomes unbalanced. Their results show that transient state response of proposed method is improved.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.3
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• pp.195-201
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• 2013

In this paper, we present optimization technique for the response time of DVR (Dynamic Voltage Restorer) and the possible compensation range of voltage dip by the DVR system. To protect 3-phase phase-controlled rectifier from voltage dip, DVR system needs to have optimum response time as an important design factor. Although the fast response time of DVR ensures wider range of voltage dip, DVR controller has so high cost and poor stability. This paper proposes DVR system with optimum response time required for certain intensity of voltage dips and good stability to support possible compensation range of voltage dip. Proposed technique showed optimum response time and good stability for overall system. We believe that proposed technique is reliable and useful in DVR design.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.335-339
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• 1999

This Paper Proposes a circuit system that is capable of rejecting the zero phase voltage produced by a inverter, which transform do-ac power using high speed power semiconductor. It generates a rejecting voltage which has the same amplitude as, but the opposite phase to the zero phase voltage. The rejecting voltage is superimposed on the load line for rejecting of the zero phase voltage through a transformer. Simulation results show that the zero phase voltage applied to the load and ground current are eliminated.

• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.157-166
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• 2016

In this paper, a new sag and peak voltage detector is proposed for a single-phase inverter using delta square operation. The conventional sag detector is from a single-phase digital phase-locked loop (DPLL) that is based on d-q transformations using an all-pass filter (APF). The d-q transformation is typically used in the three-phase coordinate system. The APF generates a virtual q-axis voltage component with a 90° phase delay, but this virtual phase cannot reflect a sudden change in the grid voltage at the instant the voltage sag occurs. As a result, the peak value is drastically distorted, and it settles down slowly. A modified APF generates the virtual q-axis voltage component from the difference between the current and the previous values of the d-axis voltage component in the stationary reference frame. However, the modified APF cannot detect the voltage sag and peak value when the sag occurs around the zero crossing points such as 0° and 180°, because the difference voltage is not sufficient to detect the voltage sag. The proposed algorithm detects the sag voltage through all regions including the zero crossing voltage. Moreover, the exact voltage drop can be acquired by calculating the q-axis component that is proportional to the d-axis component. To verify the feasibility of the proposed system, the conventional and proposed methods are compared using simulations and experimental results.

• Journal of Multimedia Information System
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• v.5 no.2
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• pp.139-142
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• 2018

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise characteristic. The proposed PLL has two charge pumps (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppresses the voltage fluctuation of LF. The PLL has a novel voltage controlled oscillator (VCO) consisting of a voltage controlled resistor (VCR) and the three-stage ring oscillator with latch type delay cells. The VCR linearly converts voltage into current, and the latch type delay cell has short active on-time of transistors. As a result, it improves phase noise characteristic. The proposed PLL has been fabricated with $0.35{\mu}m$ 3.3 V CMOS process. Measured phase noise at 1 MHz offset is -103 dBc/Hz resulting in 3 dBc/Hz phase noise improvement compared to the conventional PLL.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.8
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• pp.468-476
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• 2000

Nowadays, ozone is mainly utilized for water treatment and home equipments. Although the demand for ozone is increasing, the ozone yield of silent discharge type ozonizer is low. Therefore, it is expected to improve the energy efficiency and ozone yield of an ozonizer. In this paper, a new ozone generation system is proposed. The 60[Hz] three-phase voltage is applied to three-phase superposed discharge type ozonizer(3PSDO) which has three electrodes(central, internal and external electrodes). There is no discharge pause time when three-phase voltage is applied due to 120-degree phase difference of applied voltage. The synergy effect of the three-phase superposed discharge type ozonizer is investigated by comparing with the three sort of single-phase discharge type ozonizer(1PDO). So, three-phase superposed discharge type ozonizer is able to obtain high ozone yield, and optimize discharge space, because this can increase the discharge power at low applied voltage.

• Proceedings of the KIEE Conference
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• summer
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• pp.791-793
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• 2004

Voltage unbalance is generated by the load and impedance mismatching at the 3-phase 4-wire system of customer load. Voltage unbalance factor can be changed by the voltage amplitude or phase angle, and both. A small voltage unbalance is connected to high current unbalance. If the voltage unbalance is generated at the joint system of 1-phase and 3-phase load, Induction motor due to the current unbalance increase is generated loss, noise and torque ripple. In order to analyze the effect by voltage unbalance, it is necessary to the consideration of amplitude and phase angle. In this paper, We analyzed the effects that induction motor is affected by asymmetric voltage unbalance

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.05a
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• pp.74-77
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• 2005

Most of the loads in industrial power distribution systems are balanced and connected to three power systems. However, voltage unbalance is generated at the user's 3-phase 4-wire distribution systems with single & three phase. Voltage unbalance is mainly affected by load system rather than power system. Unbalanced voltage will draws a highly unbalanced current and results in the temperature rise and the low output characteristics at the machine. It is necessary to analyse correct voltage unbalance factor for reduction of side effects in the industrial sites. Voltage unbalance is usually defined by the maximum percent deviation of voltages from their average value, by the method of symmetrical components or by the expression in a more user-friendly form which requires only the three line voltage readings. If the neutral point is moved at the 3-phase 4-wire system by the unbalanced load, by the conventional analytical method, line and phase voltage unbalance leads to different results due to zero-sequence component. This paper presents a new analytical method for phase and line voltage unbalance factor in 4-wire systems. Two methods indicate exact results.

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.2
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• pp.94-100
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• 2018

Generally, in a single-phase energy storage system (ESS) for households, AC ripple component with twice the fundamental frequency exists inevitably in the DC link voltage of single-phase PCS. In the grid-connected mode of a single-phase inverter, the AC ripple component in the DC link voltage causes low-order harmonics on grid-side current that deteriorates power quality on an AC grid. In this work, a control system adopting a feedforward controller is established to eliminate the AC ripple interference on the DC link side. Optimal battery nominal voltage design method is also proposed by considering the voltage loss and AC ripple voltage on DC link side in a single-phase ESS. Finally, the control system and battery nominal voltage design method are verified through simulations and experiments.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.51 no.9
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• pp.460-466
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• 2002

A reliable fault phase selection algorithm plays a very important role in transmission line protection, Particularly in Extra High Voltage (EHV) networks. The conventional fault phase selection algorithm used the phase difference between positive and negative sequence current excluding load current. But, it is difficult to pick out only fault current since we can not know when a fault occurs and select the fault phase in weak-infeed conditions that dominate zero-sequence current in phase current. The proposed algorithm can select the accurately fault phase using the sum of unit vectors which are calculated by positive-sequence voltage and negative-sequence voltage.