• Journal of Power Electronics
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• v.16 no.6
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• pp.2024-2034
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• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

• Information and Communications Magazine
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• v.28 no.11
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• pp.9-15
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• 2011

CMOS 집적회로기술의 발달로 인해 디지털회로는 속도향상 소모전력 감소로 성능이 매우 많이 향상되었지만, Analog/RF 회로는 동작전압감소, 공정변화심화 등으로 인해 심각한 성능저하가 나타나고 있다. 이에 기존의 전하펌프 기반 아날로그 PLL에 대한 대안으로 All Digital PLL(ADPLL)이 개발되고 이미 상용제품에 적용되고 있다. 하지만 그 성능은 데이터변환 회로인 TDC와 DCO의 제한된 해상도로 인해 개선이 많이 필요하다. 이 두 회로는 ADPLL의 성능에 가장 큰 영향을 미치므로 본 논문에서는 지금까지 발표된 TDC와 DCO 구현사례를 중심으로 ADPLL의 연구개발동향을 살펴보고자 한다.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1233-1236
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• 2003

This paper proposes a phase-locked loop (PLL) that achieves one-cycle lock acquisition by employing the lock-acquisition circuit (LAC). The LAC produces the initial analog voltage ( v$_{c}$ ) that corresponds to the input frequency. When the transfer curve of the LAC matches that of the voltage-controlled oscillator (VCO), one-cycle locking can be possible. By HSPICE simulations, the proposed LAC is proved to be applicable to any kinds of PLL [1][2][3].].

• The KIPS Transactions:PartC
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• v.11C no.6 s.95
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• pp.835-842
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• 2004

In this paper, we have analyzed the MC-DS/CDMA system with input signal synchronized completely through adjustment of the gain in the PLL loop, by using the hybrid SC/MRC-(2/3) technique, which is said to one of the optimal diversity techniques under the multi-path fading environment, assuming that phase error is defined to the phase difference between the received signal from the multi-path and the reference signal in the PLL of the receiver. Also, assuming that the regarded radio channel model for the mobile communication is subject to the Nakagami-m fading channel, we have developed the expressions and performed the simulation under the consideration of various factor, in the MC/DS-CDMA system with the hybrid SC.MRC-(2/3) diversity method, such as the Nakagami fading index(m), $the\;number\;of\;paths\;(L_p),$ the number of hybrid SC.MRC-(2/3) $diversity\;branches\;(L,\;L_c),$ the number of users (K), the number of subcarriers (U), and the gain in the PLL loop. As a result of the simulation, it has been confirmed that the performance improvement of the system can be achieved by adjusting properly the PLL loop in order for the MC/DS-CDMA system with the hybrid SC/MRC-(2/3) diversity method to receive a fully synchronized signal. And the value of the gain in the PLL loop should exceed 7dB in order for the system to receive the signal with prefect synchronization, even though there might be a slight difference according to the values of the fading index and the spread processing gain of the subcarrier.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.4
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• pp.69-77
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• 2012

We propose a PLL-type position control method for step motors. Our control method considerably improves the instability problem at rapid acceleration or deceleration, which is a major problem of conventional open loop control methods. Moreover, our controller reduces the steady state position error to zero and guarantees lower vibration and acoustic noise at high speed. Also, our controller can produce more torque at high speed, and hence it can extend the controllable velocity range. To demonstrate the practical significance of our control method, we present some simulation results for a commercially available step motor using Simulink.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2625-2628
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• 2003

Phase locked loops are widely used in many applications such as frequency synthesis, clock/data recovery and clock generation. In nearly all the PLL applications, low jitter and fast locking time is required. Without using adaptive loop filter, this paper proposes very simple method for improving locking time and jitter reduction simultaneously in charge pump PLL(CPPLL) using Daul Phase/Frequency Detector(Dual PFD). Based on the proposed scheme, the lock time is improved by 23.1％, and the jitter is reduced by 45.2％ compared with typical CPPLL.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.466-468
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• 2008

본 논문에서는 불평형, 고조파, 잡음 등에 의해 왜곡된 3상 전원으로부터 정확한 위상각을 검출하는 PLL(Phase Locked Loop) 방법을 제안한다. 역상분과 고조파를 포함하는 왜곡된 3상 전원을 동기좌표계 d-q축 전압으로 변환하면 기본파 성분에 의한 일정한 d-q축 전압에 역상분과 고조파에 의한 맥동이 포함된 형태의 전압이 된다. 상태관측기는 이러한 전압에서 맥동성분을 제거하고 기본파 전압만 추출하여 이를 동기좌표계 PLL의 입력으로 사용함으로써 왜곡된 전원조건에서도 정확한 위상각을 검출할 수 있다. 시뮬레이션을 통해 제안된 방법의 성능을 검증하였다.

• Journal of Institute of Control, Robotics and Systems
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• v.11 no.6
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• pp.496-501
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• 2005

This paper presents experimental results of the frequency offset locking of He-Ne lasers and the stability analysis. The master laser is free running, and the slave laser is a single-mode operating laser. The frequency difference of two lasers is stabilized to 200 MHz which can be synchronized using PLL servo. The measured beat frequency between two lasers was 200.004 MHz ${\pm}$ 0.15 MHz. The square root of Allan variance as a measure of stability in time domain is also measured. The long-term stability of the beat was worse than sort-term stability. With a gate time $\tau=1000\;s$, the square root of Allan variance was about 1 GHz. The results of the square root of Allan variance of the stabilized beat signal was a gate time of $\tau=1000\;s$, the square root of Allan variance was about 1.5 kHz. The long-term stability was improved by more than several hundred times compared with that without the stabilization.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1152-1160
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• 2003

Start The current paper proposes an improved HD(High Definition) monitor that can support a signal input with various resolutions. Due to the inadequate performance of the built-in digital PLL(Phase-locked Loop) of an ADC(Analog to Digital Converter) and poor tolerance of ADC ICs, there are problems in the stable processing of synchronization signals with various input signals. Accordingly, the proposed synchronization signal optimization technique regenerates the horizontal synchronization signal in the vertical blanking interval based on the regularity of the synchronization signal, i.e. the timing of the falling edge signal remains constant, thereby solving the above problem and minimizing the interference of the system. As a result, the proposed system can stabilize various synchronization signals with different resolution modes.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.3
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• pp.283-289
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• 2018

A PLL with an unipolar charge pump and a loop filter consisting of sample-hold capacitor and Fvco-sampled feedforward loop filter. The proposed PLL not only reduces the chip area by replacing the resistance to a switch and a small capacitor but also reduces the variation of ${\Delta}VLPF$ and ${\Delta}{\Delta}VLPF$ to 1/6 and 1/5 respectively. The variation of ${\Delta}VLPF$ is related to the phase noise of VCO output and that of ${\Delta}{\Delta}VLPF$ is proportional to reference spurs. It has been simulated and verified with a 1.8V $0.18{\mu}m$ CMOS process and shown a good phase noise characteristics. We plan to fabricate chip based on the simulations and check performance.