• Journal of IKEEE
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• v.18 no.4
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• pp.586-592
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• 2014

In this paper, high efficiency power management IC(PMIC) with DT-CMOS(Dynamic threshold voltage Complementary MOSFET) switching device is presented. PMIC is controlled PWM control method in order to have high power efficiency at high current level. The DT-CMOS switch with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuit consist of a saw-tooth generator, a band-gap reference(BGR) circuit, an error amplifier, comparator circuit, compensation circuit, and control block. The saw-tooth generator is made to have 1.2MHz oscillation frequency and full range of output swing from supply voltage(3.3V) to ground. The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on current mode PWM control circuits and low on-resistance switching device, achieved the high efficiency nearly 96% at 100mA output current. And Buck converter is designed along LDO in standby mode which fewer than 1mA for high efficiency. Also, this paper proposes two protection circuit in order to ensure the reliability.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.26-36
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• 2014

The needs of active phased arrays antenna system is getting more increased for IMT-Advanced system efficiency. The active phased array structure consists of lots of small transceivers and radiation elements to increase system efficiency. The minimized module of high efficiency transceiver is key for system implementation. The power amplifier of transmitter decides efficiency of base-station. In this paper, we design and implement minimized module of high efficiency transceiver for IMT-Advanced active phased array system. The temperature compensation circuit of transceiver reduces gain error and the analog pre-distorter of linearizer reduces implemented size. For minimal size and high efficiency, the implented power amplifier consist of GaN MMIC Doherty structure. The size of implemented module is $40mm{\times}90mm{\times}50mm$ and output power is 47.65 dBm at LTE band 7. The efficiency of power amplifier is 40.7% efficiency and ACLR compensation of linearizer is above 12dB at operating power level, 37dBm. The noise figure of transceiver is under 1.28 dB and amplitude error and phase error on 6 bit control is 0.38 dB and 2.77 degree respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.1
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• pp.77-88
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• 2000

In this paper, the 3-mode variable gain high power amplifier for a transmitter of INMARSAT-B operating at L-band(1626.5-1646.5 MHz) was developed. This SSPA can amplify 42 dBm in high power mode, 38 dBm in medium power mode and 36 dBm in low power mode for INMARSAT-B. The allowable errol sets +1 dBm as the upper limit and -2 dBm as the lower limit, respectively. To simplify the fabrication process, the whole system is designed by two parts composed of a driving amplifier and a high power amplifier. The HP's MGA-64135 and Motorola's MRF-6401 were used for driving amplifier, and the ERICSSON's PTE-10114 and PTF-10021 for the high power amplifier. The SSPA was fabricated by the RP circuits, the temperature compensation circuits and 3-mode variable gain control circuits and 20 dB parallel coupled-line directional coupler in aluminum housing. In addition, the gain control method was proposed by digital attenuator for 3-mode amplifier. Then il has been experimentally verified that the gain is controlled for single tone signal as well as two tone signals. In this case, the SSPA detects the output power by 20 dB parallel coupled-line directional coupler and phase non-splitter amplifier. The realized SSPA has 41.6 dB, 37.6 dB and 33.2 dB for small signal gain within 20 MHz bandwidth, and the VSWR of input and output port is less than 1.3:1. The minimum value of the 1 dB compression point gets more than 12 dBm for 3-mode variable gain high power amplifier. A typical two tone intermodulation point has 36.5 dBc maximum which is single carrier backed off 3 dB from 1 dB compression point. The maximum output power of 43 dBm was achieved at the 1636.5 MHz. These results reveal a high power of 20 Watt, which was the design target.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.6-13
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• 2009

For X-band phased array systems, a power amplifier, a 6-bit phase shifter, a 6-bit digital attenuator, and a SPDT transmit/receive (T/R) switch are fabricated and measured. All circuits are demonstrated by using CMOS 0.18 um technology. The power amplifier has 2-stage differential and cascade structures. It provides 1-dB gain-compressed output power ($P_{1dB}$) of 20 dBm and power-added-efficiency (PAE) of 19 % at 8-11 GHz frequencies. The 6-bit phase shifter utilizes embedded switched filter structure which consists of nMOS transistors as a switch and meandered microstrip lines for desired inductances. It has $360^{\circ}$ phase-control range and $5.6^{\circ}$ phase resolution. At 8-11 GHz frequencies, it has RMS phase and amplitude errors are below $5^{\circ}$ and 0.8 dB, and insertion loss of $-15.7\;{\pm}\;1,1\;dB$. The 6-bit digital attenuator is comprised of embedded switched Pi-and T-type attenuators resistive networks and nMOS switches and employes compensation circuits for low insertion phase variation. It has max. attenuation of 31.5 dB and 0.5 dB amplitude resolution. Its RMS amplitude and phase errors are below 0.4 dB and $2^{\circ}$ at 8-11 GHz frequencies, and insertion loss is $-10.5\;{\pm}\;0.8\;dB$. The SPDT T/R switch has series and shunt transistor pairs on transmit and receive path, and only one inductance to reduce chip area. It shows insertion loss of -1.5 dB, return loss below -15 dB, and isolation about -30 dB. The fabricated chip areas are $1.28\;mm^2$, $1.9mm^2$, $0.34\;mm^2$, $0.02mm^2$, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.8 s.99
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• pp.815-824
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• 2005

In this paper, we proposed a new DGS(Defected Ground Structure) Doherty amplifier for IMT-2000 band. Originally, active load-pull analysis of a Doherty amplifier assumes ideal harmonic termination condition. However, there have been no papers considering this ideal harmonic termination condition. We obtained excellent improvements of efficiency, gain, maximum output power as well as superior size reduction of a Doherly amplifier by satisfying the overlooked assumption of ideal harmonic termination through the adaptation of DGS at the output transmission line of carrier and peaking amplifier that is essential for Doherty operation. The amount of both the 2nd and the 3rd harmonic rejection of the proposed DGS Doherty amplifier over the conventional one are 44.92 dB and over 23.77 dB, respectively. The acquired improvement in Pl dB, gain, drain efficiency, and ACPR to WCDMA 1FA signal were 0.42 dB, 0.33 dB, $6.4\%$ and 5.4 dBc, respectively. Moreover, electrical length of $90{\circ}$ is reduced at each of the DGS carrier amplifier path and DGS peaking amplifier path, therefore the whole amplifier circuit size is considerably reduced.

• Journal of Navigation and Port Research
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• v.43 no.3
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• pp.172-178
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• 2019

Although the needs for providing resilient PNT information are increasing, threats due to the intentional RFI or space weather change are challenging to resolve. eLoran, which is a terrestrial navigation system that use a high-power signal is considered as a best back-up navigation system. Depending on the user's environment in the eLoran system, the user may use one of E-field or H-field antennas. H-field antenna, which has no restriction on setting stable ground and is relatively resistant to noise of general electronic equipment, is composed of two loops, and shows anisotropic gain pattern due to the different measurement at the two loops. Therefore, the H-field antenna's phase estimation value of signal varies depending on its direction even at the static environment. The error due to the direction of the signal should be eliminated if the user want to estimate the own position more precisely. In this paper, a method to compensate the error according to the geometric distribution between the H-field antenna and the transmitting station is proposed. A model was developed to compensate the directional error of H-field antenna based on the signal generated from the eLoran signal simulator. The model is then used to the survey measurement performed in the land area and verify its performance.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.4
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• pp.148-156
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• 2009

This paper presents a new image rejection algorithm based on the analysis of the distortion of a single-frequency continuous-wave (CW) signal due to the I/Q mismatch. Existing methods estimated the gain mismatch and phase mismatch on RF receivers and compensated them However, this paper shows that the circular trajectory of a single-frequency CW signal is distorted elliptic-type trajectory due to the I/Q mismatch. Utilizing the analysis, we propose a I/Q mismatch compensation method. It has two processing steps. In the first processing step, the generated signal is rotated to align the major axis of the elliptic-type trajectory diagram with the x-axis. In the second processing step, the Q-channel signal in the regenerated signal is scaled to align the regenerated signal with the transmitted single-frequency CW signal. Simulation results show that a receiver using the proposed image rejection algorithm can achieve an image rejection ratio of more than 70dB. And, simulation results show that the bit error rate performances of receivers using the proposed image rejection algorithm are almost the same as those of conventional coherent demodulators, even in fading channels.