• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.10 s.352
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• pp.90-97
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• 2006

We report our research work on the millimeter-wave broadband amplifier integrating the shunt peaking technology with the cascode configuration. The millimeter-wave broadband cascode amplifier on MIMIC technology was designed and fabricated using $0.1{\mu}m\;{\Gamma}-gate$ GaAs PHEMT, CPW, and passive library. The fabricated PHEMT has shown a transconductance of 346.3 mS/mm, a current gain cut off frequency ($f_T$) of 113 GHz, and a maximum oscillation frequency ($f_{max}$) of 180 GHz. To prevent oscillation of designed cascode amplifier, a parallel resistor and capacitor were connected to drain of common-gate device. For expansion of the bandwidth and flatness of the gain, we inserted the short stub into bias circuits and the compensation transmission line between common-source device and common-gate device, and then their lengths were optimized. Also, the input and output stages were designed using the matching method to obtain the broadband characteristic. From the measurement, we could confirm to extend bandwidth and flat gain by integrating the shunt peaking technology with the cascode configuration. The cascode amplifier shows the broadband characteristic from 19 GHz to 53.5 GHz. Also, the average gain of this amplifier is about 6.5 dB over the bandwidth.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.262-267
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• 2005

During several method of improvement efficient, We analyzed Doherty Amplifier That used by simple circuit and 180w PEP LDMOS to analyze improvement of efficient and linearity. We for testing performance of Doherty Amplifier compared with Balanced Class AB, the experimental results show when Peaking Amp $V_gs.P$=1.53V, the efficiency is increased at Maximum 11.6$\%$. After finding optimum bias point of linearity improvement by manual tuning gate bias, when WCDMA 4FA $V_gs.P$=3.68V IMSR could be increased maximum 3.34dB. especially, when we match bias point of Peaking amp at 1.53V, we could get a excellent efficiency increase and have fUR under -3203c at output power 43dBm.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.81-86
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• 2005

In this paper, we present an efficiency extension of Doherty power amplifier using LDMOS FET devices with different peak output powers and an unequal power divider. The amplifier is designed by using a MRF21045 with P1 dB of 45 W as the main amplifier biased for Class-AB operation and a MRF21090 with P1 dB of 90 W as the peaking amplifier biased for Class-C operation. The input power is divided into a 1:1.5 power ratio between the main and peaking amplifier. The simulated results of the proposed Doherty amplifier shows an efficiency improvement of approximately 19 % in comparison to the class-AB amplifier at an output power of 42.5 dBm. The fabricated Doherty amplifier obtained a PAE of 33.68 % at 9 dB backed off from P1 dB of 51.5 dBm.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.3 no.1
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• pp.11-19
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• 1992

To design of Ultra-wideband amplifier, we analyzed the inductor peaking to reduce the capacitance effect of GaAs MESFET in upper frequency edge. And we deduced an optimun inductor peaking element from transfer function of GaAs MESFET small-signal equivalent circut and realized the Feedback Amplifier Module (FAM) having flat gain. We design the imput and output impe dance matching networks by Real-Frequency Method. It show that the gain of designed amplifier has a 6.38dB with gain variation 0.56 at 0.1~12 GHz frequency gand by computer simu-lation.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.305-308
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• 1999

In this paper, a transimpedance optical receiver based on PIN/P-HEMT with cascoded input stage and inductor peaking technique was designed for several giga bits optical communication. Analysis of the receiver shows that cascoded input stage with inductor peaking increase bandwidth without sacrificing low frequence gain. The receiver achieved a low noise characteristic and maximally flat frequence response. It is shown that the 3-dB bandwidth of the designed receiver is 8.3 ㎓ and input equivalent noise current is as low as 16pA/√Hz to 10㎓.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.11 s.114
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• pp.1030-1039
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• 2006

A high power and high gain Doherty amplifier is designed by using embedded driver amplifiers in the final stage. The operational characteristics of a two-stage Doherty amplifier are analyzed, as a function of the two-stage peaking amplifier gate biases. The driver stages and final output stages are implemented using two single-ended MRF21045s and a single push-pull packaged MRF5P21180, respectively. This two-stage Doherty amplifier demonstrated 27 dB gain with a PAE of 23 % at 15 W average output power.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.8
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• pp.807-813
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• 2008

The gate-biases of the Doherty power amplifier are controlled to improve the linearity performance. The linearity improvement mechanism of the Doherty amplifier is the harmonic cancellation of the carrier and peaking amplifier at the output power combining point. However, it is difficult to cancel the harmonic power for the broader power range because the condition for cancelling is varied by power. For the linearity improvement, we have explored the linearity characteristic of the Doherty amplifier according to the input power and gate biases of the carrier and peaking amplifier. To extend the region of harmonic power cancellation, we have injected the proper gate bias to the carrier and peaking amplifier according to the input power levels. To validate the linearity improvement, the Doherty amplifier is designed using Eudyna 10-W PEP GaN HEMT EGN010MKs at 2.345 GHz and optimized to achieve a high linearity and efficiency at an average output power of 33 dBm, backed off about 10 dB from the $P_{1dB}$. In the experiments, the envelope tracking Doherty amplifier delivers a significantly improved adjacent channel leakage ratio performance of -37.4 dBc, which is an enhancement of about 2.8 dB, maintaining the high PAE of about 26 % for the WCDMA 1-FA signal at an average output power of 33 dBm. For the 802.16-2004 signal, the amplifier is also improved by about 2 dB, -35 dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.158-165
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• 2013

In this paper, a new circuit topology of an ultra-wideband (UWB) 3.1-10.6GHz CMOS low noise amplifier is presented. The proposed UWB low noise amplifier is designed utilizing RC feedback and LC filter networks which can provide good input impedance matching. In this design, the current-reused topology is adopted to reduce the power consumption and the inductor-peaking technique is applied for the purpose of bandwidth extension. The performance results of this UWB low noise amplifier simulated in $0.18-{\mu}m$ CMOS process technology exhibit a power gain of 14-14.9dB, an input matching of better than -10.8dB, gain flatness of 0.9dB, and a noise figure of 2.7-3.3dB in the frequency range of 3.1-10.6GHz. In addition, the input IP3 is -5dBm and the power consumption is 12.5mW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.9 s.100
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• pp.957-963
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• 2005

This paper presents technique of wideband TIA for optical communication systems using TSMC 0.25 ${\mu}m$ CMOS RF-Mixed mode. In order to improve bandwidth characteristics of an TIA, we use active inductor shunt peaking to cascode and common-source configuration. The result shows the 37 mW and 45 mW power dissipation with 2.5 V bias and 61 dB$\Omega$ and 61.4 dB$\Omega$ transimpedance gain. And the -3 dB bandwidth of the TIA is enhanced from 0.8 GHz to 1.45 GHz in cascode and 0.61 GHz to 0.9 GHz in common-source. And the input noise current density is $5 pA/\sqrt{Hz}$ and $4.5 pA/\sqrt{Hz}$, and -10 dB out put return loss is obtained in 1.45 GHz. The total size of the chip is $1150{\times}940{\mu}m^2$.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.403-408
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• 2008

In this paper, the high efficiency and linearity Doherty power amplifier using DGS and adaptive bias technique has been designed and realized for 2.3GHz WiBro applications. The Doherty amplifier has been implemented us-ing silicon MRF 281 LDMOS FET. The RF performances of the Doherty power amplifier (a combination of a class AB carrier amplifier and a bias-tuned class C peaking amplifier) have been compared with those of a class AB amplifier alone, and conventional Doherty amplifier. The Maximum PAE of designed Doherty power amplifier with DGS and adaptive bias technique has been 36.6% at 34.01dBm output power. The proposed Doherty power amplifier showed an improvement 1dB at output power and 7.6% PAE than a class AB amplifier alone.