• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.886-888
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• 1993

Recently current mode control is widely adopted in switching power converter because of inherent stablity and ability of parallel operating. There are several ways in current mode control. One of them, peak current control is chiefly employed. Peak current mode control converter usually senses and controls peak inductor current. But there is peak-to-average current errors. Therefore peak current control needs compensation ramp correcting the errors. Average current mode control eliminates these problems, and is constructed by simple structures. This paper will describe the behavior of a simple average current mode boost converter and introduce the design techniques.

• Journal of Power Electronics
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• v.19 no.3
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• pp.613-624
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• 2019

Digital current control techniques are an attractive option for DC-DC converters. In this paper, a digital predictive peak current control algorithm is presented for buck converters that allows the inductor current to track the reference current in two switching cycles. This control algorithm predicts the inductor current in a future period by sampling the input voltage, output voltage and inductor current of the current period, which overcomes the problem of hardware periodic delay. Under the premise of ensuring the stability of the system, the response speed is greatly improved. A real-time parameter identification method is also proposed to obtain the precision coefficient of the control algorithm when the inductance is changed. The combination of the two algorithms achieves adaptive tracking of the peak inductor current. The performance of the proposed algorithms is verified using simulations and experimental results. In addition, its performance is compared with that of a conventional proportional-integral (PI) algorithm.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.4
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• pp.338-345
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• 1998

The mathematical interpretation of a practical sampler which is useful to obtain the small signal models for the peak and average current mode controls is proposed. Due to the difficulties in applying the Shannons sampling theorem to the analysis of sampling effects embedded in the current mode control, several different approaches have been reported. However, these approaches require the information of the inductor current in a discrete expression, which restricts the application of the reported method only to the peak current mode control. In this paper, the mathematical expressions of sampling effects on a current loop which can directly apply the Shannons sampling theorem are newly proposed, and applied to the modeling of the peak current mode control. By the newly derived models of a practial smapler, the models in a discrete time domain and a continuous time domain are obtained. It is expected that the derived models are useful for the control loop design of power supplies. The effectiveness of the derived models are verified through the simulation and experimental results.

• Journal of Electrical Engineering and Technology
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• v.10 no.5
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• pp.1989-2000
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• 2015

In this paper, digital peak current mode control for single phase H-bridge inverters is developed and implemented. The digital peak current mode control is achieved by directly controlling the PWM signals by cycle-by-cycle current limitation. Unlike the DC-DC converter where the output voltage always remains in the positive region, the output of DC-AC inverter flips from positive to negative region continuously. Therefore, when the inverter operates in negative region, the control should be changed to valley current mode control. Thus, a novel control logic circuit is required for the function and need to be analyzed for the hardware to track the sinusoidal reference in both regions. The problem of sub-harmonic instability which is inherent with peak current mode control is also addressed, and then proposes the digital slope compensation in constant-sloped external ramp to suppress the oscillation. For unipolar PWM switching method, an adaptive slope compensation in digital manner is also proposed. In this paper, the operating principles and design guidelines of the proposed scheme are presented, along with the performance analysis and numerical simulation. Also, a 200W inverter hardware prototype has been implemented for experimental verification of the proposed controller scheme.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.2
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• pp.301-307
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• 2009

In the paralleled converter module with peak current mode control, current imbalance appears when the voltage controllers with integral control of converter module are not exactly identical. In this paper, the voltage controller is designed to equal the current command of each converter module using the current command bus. The current balance controller is also proposed to balance the average currents of converter modules with imbalaced inductance. It is designed to have good transient response. Proposed method is implemented with the paralleled 2-module and 4-module boost converters with imbalanced inductance. Experimental results verify the performance of current share during both steady and transient states of converter.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.2
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• pp.134-137
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• 2019

A wide-bandwidth current controller is required for fast charging/discharging of super capacitor applications. Peak current mode is generally used to accomplish fast charging/discharging because this mode has fast response characteristics. However, the peak current mode control must have a slope compensation function to restrain sub-harmonics oscillation. The slope must be changed accordingly if the controlled output voltage is varied. However, changing the slope for every changed output voltage is not easy. The other solution, selecting the slope as the maximum value, causes a slow response problem to occur. Therefore, we propose a hybrid mode controller that uses a peak current and a newly specified valley current. Through the proposed hybrid mode control, the sub-harmonic oscillation does not occur when the duty is larger than 0.5 because of the fast response.

• Proceedings of the KIPE Conference
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• 1998.07a
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• pp.275-278
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• 1998

The mathematical interpretation of a practical sampler which is useful to obtain the small signal models for the peak and average current mode controls is proposed. Due to the difficulties in applying the Shannon's sampling theorem to the analysis of sampling effects embedded in the current mode control, several different approaches have been reported. However, these approaches require the information of the inductor current in a discrete expression, which restricts the application of the reported method only to the peak current mode control. In this paper, the mathematical expressions of sampling effects on a current loop which can directly apply the Shannon's sampling theorem are newly proposed, and applied to the modeling of the peak current mode control. By the newly derived models of a practical sampler, the models in a discrete time domain and a continuous time domain are obtained. It is expected that the derived models are useful for the control loop design of power supplies. The effectiveness of the derived models are verified through the simulation and experimental results.

• Proceedings of the KIPE Conference
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• 1998.07a
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• pp.154-157
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• 1998

In this paper, the inverter TIG(Tungsten Inert Gas) welding system with high power efficiency by means of pulse current control of welding process is presented. In TIG welding, pulse current control is utilized in order to attain less apatter and high welding performance. The four factors which determine the welding performance of the pulse current are frequency, base current, peak current, and peak current duty current, and peak current duty ratio. In this paper, we analyze these factors should be controlled to achieve minimum power input. To demonstrate the practical significance of our results, we present some experimental results as well as simulation results.

• Journal of Power Electronics
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• v.12 no.5
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• pp.715-722
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• 2012

New discrete time domain models for the peak current controlled (PCC) power LED drivers in continuous conduction mode include for the first time the effects of the time delay in the pulse-width-modulator. Realistic amounts of time delay are found to have significant effects on the average output LED current and on the critical inductor value at the boundary between the two conduction modes. Especially, the time delay can provide an accurate LED current for the PCC buck converter with a wide input voltage. The models can also predict the critical inductor value at the mode boundary as functions of the input voltage and the time delay. The overshoot of the peak inductor current due to the time delay results in the increase of the average output current and the reduction of the critical inductor value at the mode boundary in all converters. Experimental results are presented for the PCC buck LED driver with constant-frequency controller.

• ETRI Journal
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• v.36 no.5
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• pp.876-879
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• 2014

In current NAND flash design, one of the most challenging issues is reducing peak current consumption (peak ICC), as it leads to peak power drop, which can cause malfunctions in NAND flash memory. This paper presents an efficient approach for reducing the peak ICC of the cache program in NAND flash memory - namely, a program Cache Busy Time (tPCBSY) control method. The proposed tPCBSY control method is based on the interesting observation that the array program current (ICC2) is mainly decided by the bit-line bias condition. In the proposed approach, when peak ICC2 becomes larger than a threshold value, which is determined by a cache loop number, cache data cannot be loaded to the cache buffer (CB). On the other hand, when peak ICC2 is smaller than the threshold level, cache data can be loaded to the CB. As a result, the peak ICC of the cache program is reduced by 32% at the least significant bit page and by 15% at the most significant bit page. In addition, the program throughput reaches 20 MB/s in multiplane cache program operation, without restrictions caused by a drop in peak power due to cache program operations in a solid-state drive.