• Korean Journal of Microbiology
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• v.54 no.4
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• pp.325-329
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• 2018

Thp1/PCID2, PCI domain-containing protein, is a component of the evolutionally conserved TREX-2 complex linking mRNA transcription and export. In fission yeast, Schizosaccharomyces pombe, the pci2 (SPBC1105.07c) gene encodes a PCI domain-containing protein that is predicted as a fission yeast orthologue of Thp1 (in budding yeast)/PCID2 (in human). Repression of pci2 expression inhibited both growth and mRNA export. And over-expression of pci2 also exhibited growth retardation with slight accumulation of $poly(A)^+$ RNA in the nucleus. Moreover, yeast two-hybrid and co-immunoprecipitation analysis showed that the Pci2 protein physically interacted with Sac3 and Dss1, which are members of TREX-2 complex. These observations support that the S. pombe Pci2 protein, as a component of TREX-2 complex, is implicated in mRNA export.

• The KIPS Transactions:PartA
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• v.12A no.6 s.96
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• pp.523-530
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• 2005

When a PCI 2.2 bus master requests data using Memory Read command, a target device may hold PCI bus without data to be transferred for long time because a target device needs time to prepare data infernally. Because the usage efficiency of the PCI bus and the data transfer efficiency are decreased due to this situation, the PCI specification recommends to use the Delayed Transaction mechanism to improve the system performance. But the mechanism cann't fully improve performance because a target device doesn't know the exact size of prefetched data. In the previous work, we propose a new method called Prefetch Request when a bus master intends to read data from the target device. In this paper, we design PCI 2.2 controller and local device that support the proposed method. The designed PCI 2.2 controller has simple local interface and it is used to convert the PCI protocol into the local protocol. So the typical users, who don't know the PCI protocol, can easily design the PCI target device using the proposed PCI controller. We propose the basic behavioral verification, hardware design verification, and random test verification to verify the designed hardware. We also build the test bench and define assembler instructions. And we propose random testing environment, which consist of reference model, random generator ,and compare engine, to efficiently verify corner case. This verification environment is excellent to find error which is not detected by general test vector. Also, the simulation under the proposed test environment shows that the proposed method has the higher data transfer efficiency than the Delayed Transaction about $9\%$.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.1671-1674
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• 2005

PCI 2.2 마스터 디바이스가 타겟 디바이스로부터 데이터를 읽어 오고자 할 때 타겟 장치는 내부적으로 데이터를 준비해야 함으로 인해 PCI 버스가 데이터 전송 없이 점유되는 상황이 발생한다. 이를 위해 PCI 2.2 사양에서는 지연전송을 제안하여 전송 효율을 향상시켰지만 이 역시 타겟 디바이스가 얼마의 데이터를 미리 준비 해둘지를 알 수 없어 인해 버스 사용 및 데이터 전송 효율을 떨어뜨리는 원인을 제공한다. 본 논문에서는 먼저 이를 해결하기 위한 새로운 방법을 제안한다. 그리고 이 방법을 지원하는 PCI 타겟 컨트롤러와 로컬 디바이스를 설계하였다. 설계되어진 PCI 타겟 컨트롤러는 PCI 2.2를 전혀 모르는 사용자도 쉽게 PCI 인터페이스를 지원할 수 있도록 한 프로토콜 변환기로 사용될 수 있다. PCI 타겟 컨트롤러와 로컬 디바이스는 먼저 행위 모델로 설계하였으며 또한 이들을 검증하기 위한 테스트벤치를 설계 하였다. 이를 통해 제안되어진 방법의 성능을 측정하였으며 후에 다시 실제 하드웨어로 설계하였다. 설계되어진 하드웨어를 효과적으로 검증하기 위해 참조모델, 랜덤발생기, 비교엔진으로 구성된 랜덤 테스트 환경을 제안하였다. 이 검증 환경에서 수행된 결과를 비교함으로써 일반적인 테스트 벡터에서 발견하기 어려운 에러들을 발견할 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.4
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• pp.1-8
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• 2004

When the PCI 2.2 bus master requests data using Memory Read command, the target device my hold PCI bus without data transfer for a long time because the target device requires time to prefetch data internally. Because the PCI bus usage efficiency and the data transfer efficiency are decreased due to this situation, the PCI specification recommends to use the Delayed Transaction mechanism to improve the performance. But the mechanism doesn't fully improve performance because the target device doesn't blow prefetch data size exactly. In this paper, we propose a new method to transfer data efficiently when the bus master reads data from the target device. The bus master informs the target device the exact read data size using prefetch request using Memory Write command. The simulation result shows that the proposed method has the higher data transfer efficiency than the Delayed Transaction about 10%.

• Journal of Satellite, Information and Communications
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• v.8 no.1
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• pp.54-60
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• 2013

The need for high performance of on-board computer (OBC) is essential due to the growing requirements and diversified missions, and so OBC has been developed on the basis of the standard design and reconfigurable modularization in order to improve the utilization of OBC for different missions. The processor in OBC of next generation satellite which is currently developed by KARI is adopted the LEON2-FT/AT697F processor based SPARC v8 as main processor and controls various devices such as SpaceWire, MIL-STD-1553B and CAN through PCI on the standardized communication chips. This paper presents the architecture and design of system software for LEON2-FT processor based on PCI, and development of PCI software component. Also it describes the porting of VxWorks 6.5 for LEON2-FT and the test under the simulation environment for LEON2-FT and PCI with communication chips.

• Journal of Medicine and Life Science
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• v.19 no.2
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• pp.46-56
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• 2022

The incidence of fever complicating percutaneous coronary intervention (PCI) is rare. However, little is known regarding the cause of fever after PCI. Therefore, this study aimed to determine the clinical characteristics of patients with acute myocardial infarction (AMI), with or without fever, after PCI. We enrolled a total of 926 AMI patients who underwent PCI. Body temperature (BT) was measured every 4 hours or 8 hours for 5 days after PCI. Patients were divided into two groups according to BT as follows: BT<37.7℃ (no-fever group) and BT ≥37.7℃ (fever group). The 2 years clinical outcomes were compared subsequently. Fever after PCI was associated with higher incidence of major adverse cardiac events (MACE) (hazard ratio [HR], 1.56; 95% confidence interval [CI], 1.07-2.28; P=0.021), all-cause death (HR, 2.32; 95% CI, 1.18-4.45; P=0.014), cardiac death (CD) (HR, 2.57; 95% CI, 1.02-6.76; P=0.049), and any revascularization (HR, 1.69; 95% CI, 1.02-2.81; P=0.044) than without fever. In women, prior chronic kidney disease, lower left ventricular (LV) ejection fraction, higher LV wall motion score index, white blood cell count, peak creatine kinase-myocardial band level, and longer PCI duration were associated with fever after PCI. Procedures such as an intra-aortic balloon pump, extracorporeal membrane oxygenation, continuous renal replacement therapy, central and arterial line insertion, and cardiopulmonary resuscitation were related to fever after PCI. Fever after PCI in patients with AMI was associated with a higher incidence of MACE, all-cause death, CD, and any revascularization at the 2 years mark than in those without fever.

• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.1
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• pp.9-16
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• 2007

본 논문에서는 차세대 통신 플랫폼을 위한 PCI 익스프레스의 전송계층과 데이터 연결계층의 모든 기능을 지원하는 PCI 익스프레스 컨트롤러를 설계하였다. 설계된 컨트롤러를 효과적으로 제어하기 위해 8051 마이크로프로세서를 이용하였다. 또한, 본 논문에서는 PCI 익스프레스 컨트롤러와 8051 마이크로프로세서의 통합 검증을 위한 방법으로 벡터 생성 부분, 테스트 벤치, 그리고 메모리로 구성된 테스트 벤치를 하나의 가상 마이크로프로세서로 가정하였다. 그리고 PCI 익스프레스의 모든 프로토콜을 지원할 수 있는 어셈블리 수준의 명령어들을 테스트 벤치에 적용되도록 하였다. 특히 일반적인 기본 동작 검증과 설계 기반 검증에서 찾지 못한 특수 경우의 에러를 찾기 위한 검증을 위해 랜덤 검증 환경 및 테스트 파라미터를 정의 하였다. 제안된 검증 환경과 명령어를 통해 설계된 PCI 컨트롤러의 검증 결과 랜덤 테스트 검증을 통해 효과적으로 오류를 찾을 수 있었다.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.811-814
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• 2003

Today's and tomorrow's processors and I/O devices are demanding much higher I/O bandwidth than PCI 2.3 or PCI-X can deliver and it is time to engineer a new generation of PCI to serve as a standard I/O bus for future generation platforms. According to this demand the PCI SIG proposed PCI Express. This paper describes about the design of PCI Express Behavioral Model. A Behavioral Model enables the designers to test whether the design specifications are met by performing computer simulations rather than experiments on the physical prototype. In the proposed Model, we can verify whether our design concept satisfies the PCI Express functional protocol.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.807-810
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• 2003

The PCI 2.2 spec introduces Delayed Transaction mechanism to improve system performance for target device with slow local bus. But this mechanism has some restriction since target device doesn't know prefetch data size. So, we propose a new mechanism, which target device prefetch exact data on local bus, to improve data rate on PCI or local interface. The simulation results showed that the proposed mechanism more improves system performance than the Delayed Transaction mechanism.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.2
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• pp.199-207
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• 2014

Although High-altitude electromagnetic pulse(HEMP) protection filter meets the requirements of pulsed current injection(PCI) acceptance test, the equipment under test which has low electromagnetic susceptibility level can be damaged during PCI verification test that is performed on operating condition of equipment. This paper proposed the HEMP effect analysis method using comparison of norms between residual current of HEMP filter and transient electromagnetic conducted susceptibility criteria of equipment, as an alternative method under the condition that performing PCI verification test is limited in HEMP hardened facilities. PCI acceptance test of HEMP filter, transient electromagnetic conducted susceptibility test, and PCI verification test are performed and test results are analyzed.