• 한국정보통신학회논문지
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• 제17권8호
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• pp.1899-1907
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• 2013

본 논문에서는 초미세 패턴으로 구성된 칩-온-필름(Chip-on-Film, COF) 패키징 작업에서 발생하는 결함들을 참조영상에 기초하여 효율적으로 검출하고 분류하는 시스템을 제안한다. COF패키징 제작 과정에서 발생하는 치명적인 결함은 개방(open), 일부개방(mouse bite, near open), 단락(hard short) 및 돌기(protrusion, near short, soft short) 등을 포함한다. 이러한 결함을 검출하기 위해서는 기존에 직접 육안으로 식별하거나 또는 전기회로 설계를 이용하는 방법을 사용하였다. 그러나 이러한 방법은 매우 많은 시간과 고비용이 요구되는 단점이 있다. 본 논문에서는 참조영상을 사용하여 효과적으로 결함유무를 판단하고 결함이 발생되는 경우에 결함의 종류를 4 가지 형태로 분류하는 시스템을 제안한다. 제안방식은 검사영상의 전처리, 관심영역 추출, 지역이진분석에 의한 이물 특징 분석과 분류 등을 포함한다. 수많은 실험을 통해, 제안된 시스템은 초미세 패턴을 가진 COF의 결함 검사 및 분류에 대해 기존의 방식에 비해 시간과 경비를 줄이는데 효과적임을 보인다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1149-1152
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• 2003

Now a days, many different kinds of display technologies such as Liquid Crystal Display (LCD), Organic Light Emitting Diode (OLED), and Liquid Crystal On Silicon (LCOS) are designed. And these display technologies will be used in many application products like High Definition Televisions (HDTVs) or mobile devices. In this paper, pattern generation circuit for display test is proposed. The proposed circuit will be embedded in the control circuit of display chip. Two differenct kinds of patterns is generated by the circuit. One is block pattern for color test, and the other is line pattern for pixel test. The shape of test pattern is determined by the values of registers in pattern generation circuit. The circuit is designed using Verilog HDL RTL code.

• Transactions on Electrical and Electronic Materials
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• 제16권6호
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• pp.312-316
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• 2015

Through silicon via (TSV) technology holds the promise of chip-to-chip or chip-to-package interconnections for higher performance with reduced signal delay and power consumption. It includes high aspect ratio silicon etching, insulation liner deposition, and seamless metal filling. The desired etch profile should be straightforward, but high aspect ratio silicon etching is still a challenge. In this paper, we investigate the use of etch hard mask for finer TSVs etching to have clear definition of etched via pattern. Conventionally employed photoresist methods were initially evaluated as reference processes, and oxide and metal hard mask were investigated. We admit that pure metal mask is rarely employed in industry, but the etch result of metal mask support why hard mask are more realistic for finer TSV etching than conventional photoresist and oxide mask.

• Journal of Welding and Joining
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• 제25권2호
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• pp.76-81
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• 2007

Solder bumps have been used to interconnect the chip and substrate, and the size of the solder bump decreases below $100{\mu}m$ to accommodate higher packaging density. In order to fabricate solder bumps, a mold to chip transfer process is suggested in this work. Since the thin stainless steel mold is not wet by the solder, the molten solder is forced to fill the mold cavities with ultrasonic vibration. The solders within the mold cavities are transferred to the Cu pads on the polyimide film through reflow soldering.

• 한국조명전기설비학회지:조명전기설비
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• 제3권2호
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• pp.63-68
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• 1989

정지형 전원(Static Power Supply) 설계를 위한 다중 PAM 인버터에 관하여 논한다. 인버터의 제어부는 원칩 마이크로 컴퓨터(One-chip Microcomputer)로 구성하여 간단히 제어신호를 얻었고, 종단 구성은 더블 브리지 인버터와 3상 3권선 변압기로 구성하였다. 출력 파형은 제어기와 변압기를 이용하여 1주기당 22 스텝의 전압레벨로 다중 PAM파형을 합성하였으며, 저역 여파기(Low Pass Filter)에 의해 정현파에 가까운 파형을 얻었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.309-312
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• 2001

A primitive gas classification system which can classify limited species of gas was designed and simulated. The 'electronic nose' consists of an array of 4 metal oxide gas sensors with different selectivity patterns, signal collecting unit and a signal pattern recognition and decision Part in PLD(programmable logic device) chip. Sensor array consists of four commercial, tin oxide based, semiconductor type gas sensors. BP(back propagation) neutral networks with MLP(Multilayer Perceptron) structure was designed and implemented on CPLD of fifty thousand gate level chip by VHDL language for processing the input signals from 4 gas sensors and qualification of gases in air. The network contained four input units, one hidden layer with 4 neurons and output with 4 regular neurons. The 'electronic nose' system was successfully classified 4 kinds of industrial gases in computer simulation.

• 전자공학회논문지A
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• 제33A권11호
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• pp.128-139
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• 1996

In this paper, we propose an algorithm to solve the problem of placement of rectangular blocks whose sizes and shpaes are pre-determined. The proposed method solves the placement of many retangular blocks of different sizes and shapes in a hierarchical manner, so as to minimize the chip area. The placement problem is divided into several sub-problems: hierarchical partioning, hierarchical area/shape estimation, hierarchical pattern pacement, overlap removal, and module rotation. After the circuit is recursively partitioned to build a hierarchy tree, the necessary wiring area and module shpaes are estimated using the resutls of the partitioning and the pin information before the placement is performed. The placement templaes are defined to represent the relative positions of the modules. The area and the connectivity are optimized separately at each level of hierachy using the placement templates, so the minimization of chip area and wire length can be achieved in a short execution time. Experiments are made on the MCNC building block benchmark circuits and the results are compared with those of other published methods. The proposed technique is shown to produce good figures in tems of execution time and chip area.

• 생물정신의학
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• 제8권2호
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• pp.203-207
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• 2001

The genome sequencing project has generated and will continue to generate enormous amounts of sequence data including 5 eukaryotic and about 60 prokaryotic genomes. Given this ever-increasing amounts of sequence information, new strategies are necessary to efficiently pursue the next phase of the genome project-the elucidation of gene expression patterns and gene product function on a whole genome scale. In order to assign functional information to the genome sequence, DNA chip(or gene microarray) technology was developed to efficiently identify the differential expression pattern of independent biological samples. DNA chip provides a new tool for genome expression analysis that may revolutionize many aspects of biotechnology including new drug discovery and disease diagnostics.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.739-741
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• 1993

This paper deals with the Improvement of inverter output waveform with space vector modulation using the DSP-chip. The proposed scheme can be considered as a alternative of the conventional, subharmonic method. This scheme features a maximum output voltage that is 15% greater. The number of switchings is also 30% less than the one obtained by subharmonic modulation method(SHM) A performance function(PF) which is the time integral function of the inverter output voltage is introduced in this paper. An optimal PWM pattern is obtained by minimizing the distortion factor of performance function. The experiment was carried out with an TMS320C25.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전기물성,응용부문
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• pp.197-199
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• 2002

This paper describes the effects of chip arrangement configurations and the dimension of a reflecting cup upon the light output characteristics of a white lamp composed of RGB LED chips. As a result of simulation, the shorter distance between adjacent chips leads to a relative decrease in the light output efficiency due to inter-chip absorption of quanta, but rather uniform color mixing is expected. Among the factors of designing a reflecting cup it is the tilt angle of the cup wall that plays a determining role upon the variation of the light distribution. The light distribution shows a sudden change of pattern from Lambertian to Batwing at about $35^{\circ}{\sim}40^{\circ}$ of tilt angle in case of a silver-coated wall cup.