• Proceedings of the KIEE Conference
• /
• 1994.07a
• /
• pp.307-312
• /
• 1994

In this investigation the PFM(Pulse Frequency Modulation} will be used for optimizing PWM inverter pulse pattern. In traditional the pulse frequency of PWM is kept const. But modulated PWM's frequency in this study, the sinusoidal inverter's performance should be improved. The PWM pulsepatterns are definitely controlled so that the time-integral function of the voltage vectors in the space vector notation may show a circular locus. Further, performance index will be minimized because of minimizing distortion of output current. Finally, we will implement itusingsingle-chip microprocessor.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2002.11a
• /
• pp.67-67
• /
• 2002

패키지 기술의 개발은 저비용, 고성능, 높은 패키징 효율의 추세로 가고 있다. 이러한 추세에 따라 기판재료의 개발 및 구조의 변형이 요구된다. 패키지의 한 형태인 MCM(Multi-Chip Module)에 연성기판을 사용할 경우 fine pattern이 가능하고 부피가 작기 때문에 패키지의 효율이 좋고 또한 reel to reel process에 적용이 가능하기 때문에 대량생산의 이점을 가지고 있다. 연성기판은 좋은 전기적 특성을 가진 polyimide와 구리 층으로 구성된다. 그러나 polyimide와 구리 계층 사이에 약한 접착력과 구리로의 polyamic acid의 diffusion, 다층 기판의 제조의 어려움 등의 문제점을 남겨두고 있다. 본 연구는 일반적인 polyimide/copper가 구조가 가지고 있는 문제점을 해결하고 구리 패턴을 제작하기 위해 에칭을 쓰는 것을 배제함으로 fine pattern을 이루어 내었으며 전기도금으로 완전하게 채워진 pluged via을 사용함으로 각층간의 연결에 신뢰성을 부여하였다. 또한, 연성기판의 구조적인 문제점인 해결하여 다층 연성기판을 제조하려고 한다.

• Journal of information and communication convergence engineering
• /
• v.3 no.1
• /
• pp.28-32
• /
• 2005

In this paper, we propose a novel test method to effectively detect hard and soft faults in CMOS 2-stage op-amps. The proposed method uses a very high frequency sinusoidal signal that exceeds unit gain bandwidth to maximize the fault effects. Since the proposed test method doesn't require any complex algorithms to generate the test pattern and uses only a single test pattern to detect all target faults, therefore test costs can be much reduced. The area overhead is also very small because the CUT is converted to a unit gain amplifier. Using HSPICE simulation, the results indicated a high degree of fault coverage for hard and soft faults in CMOS 2-stage op-amps. To verify this proposed method, we fabricated a CMOS op-amp that contained various short and open faults through the Hyundai 0.65-um 2-poly 2-metal CMOS process. Experimental results for the fabricated chip have shown that the proposed test method can effectively detect hard and soft faults in CMOS op-amps.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.12
• /
• pp.2283-2288
• /
• 2006

As development in technology of bioinformatics recently makes it possible to operate micro-level experiments, we can observe the expression pattern of total genome through on chip and analyze the interactions of thousands of genes at the same time. Thus, DNA microarray technology presents the new directions of understandings for complex organisms. Therefore, it is required how to analyze the enormous gene information obtained through this technology effectively. In this thesis, We used sample data of bioinformatics core group in harvard university. It designed and implemented system that evaluate accuracy after dividing in class of two using Bayesian algorithm, ASA, of feature extraction method through normalization process, reducing or removing of noise that occupy by various factor in microarray experiment. It was represented accuracy of 98.23% after Lowess normalization.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.19 no.5
• /
• pp.493-500
• /
• 2008

This paper describes a design of internal frequency modulation(FM) radio antenna fur mobile terminal. In order to control of impedance at an operating frequency of the designed antenna, the lumped constant elements of R and L chip components are used. Patch and stubs located at antenna backside are added to control an exact resonance frequency and miniaturization. A fabricated antenna sire, the measured return loss, impedance, bandwidth, and gain are $40{\times}70{\times}1$ mm, -23 dB at 99 MHz, $55-j7{\Omega}$, 22 MHz($88{\sim}110$ MHz) below -10 dB, and -15 dBi, respectively. These measured results show a good agreement with simulated results. Especially, the measured gain of fabricated antenna is similar with value of a conventional ear-phone antenna in the designed frequency band. The measured radiation pattern agrees well with the calculated omni-directional pattern.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.7
• /
• pp.1243-1248
• /
• 2008

As development in technology of bioinformatics recently mates it possible to operate micro-level experiments, we can observe the expression pattern of total genome through on chip and analyze the interactions of thousands of genes at the same time. In this thesis, we used CDNA microarrays of 3840 genes obtained from neuronal differentiation experiment of cortical stem cells on white mouse with cancer. It analyzed and compared performance of each of the experiment result using existing DT, NB, SVM and multi-perceptron neural network classifier combined the similar scale combination method after constructing class classification model by extracting significant gene list with a similar scale combination method proposed in this paper through normalization. Result classifying in Multi-Perceptron neural network classifier for selected 200 genes using combination of PC(Pearson correlation coefficient) and ED(Euclidean distance coefficient) represented the accuracy of 98.84%, which show that it improve classification performance than case to experiment using other classifier.

• Journal of Integrative Natural Science
• /
• v.3 no.3
• /
• pp.168-173
• /
• 2010

Novel porous silicon chip exhibiting dual optical properties, both Frbry-Perot fringe (optical reflectivity) and photoluminescence had been developed and used as chemical sensors. Porous silicon samples were prepared by an electrochemical etch of p-type sillicon wafer (boron-doped, <100> orientation, resistivity 1 - 10 ${\Omega}$). The ething solution was prepared by adding an equal volume of pure ethanol to an aqueous solution of HF (48% by weight). The porous silicon was illuminated with a 300 W tungsten lamp for the duration of etch. Ething was carried out as a two-electrode Kithley 2420 preocedure at an anodic current. The surface of porous silicon was characterized by FT-IR instrument. The porosity of samples was about 80%. Three different types of porous silicon, fresh porous silicon (Si-H termianated), oxidized porous silicon (Si-OH terminated), and surface-derivatized porous silicon (Si-R terminated), were prepared by the thermal oxidation and hydrosilylation. Then the samples were exposed to the wapor of various organics vapors. such as chloroform, hexane, methanol, benzene, isopropanol, and toluene. Both reflectivity and photoluminescence were simultaneously measured under the exposure of organic wapors.

• Transactions on Electrical and Electronic Materials
• /
• v.8 no.5
• /
• pp.196-200
• /
• 2007

In this paper, we propose and discuss the design using a simple method that reduces the fixed pattern noise(FPN) generated on the amorphous Si($\alpha-Si$) bolometer. This method is applicable to an IR image sensor. This method can also minimize the size of the reference resistor in the readout integrated circuit(ROIC) which processes the signal of an IR image sensor. By connecting four bolometer cells in parallel and averaging the resistances of the bolometer cells, the fixed pattern noise generated in the bolometer cell due to process variations is remarkably reduced. Moreover an $\alpha-Si$ bolometer cell, which is made by a MEMS process, has a large resistance value to guarantee an accurate resistance value. This makes the reference resistor be large. In the proposed cell structure, because the bolometer cells connected in parallel have a quarter of the original bolometer's resistance, a reference resistor, which is made by poly-Si in a CMOS process chip, is implemented to be the size of a quarter. We designed a ROIC with the proposed cell structure and implemented the circuit using a 0.35 um CMOS process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2007.10a
• /
• pp.131-134
• /
• 2007

In this paper, we propose the 1D-CZP pattern for FPGA verification. The algorithm that was implemented by Verilog-HDL on FPGA board is verified before the chip is producted. Input through the external sensor might not be enough to verify the algorithm on FPGA board. Hence, both external input and internal input can lead the verification of the algorithm. This paper suggests the hardware implementation of compact 1D-CZP pattern that has the random input. It is useful to analyze the characteristics of the filter frequencies and organized as ROM Table which is efficient to Modulus operation.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.4
• /
• pp.405-414
• /
• 2016

IC-implementations provide high performance for solving the high computational cost of pattern matching but have relative low flexibility for satisfying different applications. In this paper, we report an associative memory architecture for k nearest neighbor (KNN) search, which is one of the most basic algorithms in pattern matching. The designed architecture features reconfigurable vector-component parallelism enabled by programmable switching circuits between vector components, and a dedicated majority vote circuit. In addition, the main time-consuming part of KNN is solved by a clock mapping concept based weighted frequency dividers that drastically reduce the in principle exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. A test chip in 180 nm CMOS technology, which has 32 rows, 8 parallel 8-bit vector-components in each row, consumes altogether in peak 61.4 mW and only 11.9 mW for nearest squared Euclidean distance search (at 45.58 MHz and 1.8 V).