• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.07b
• /
• pp.985-988
• /
• 2004

The carrier lifetime of boron doped Cz silicon samples after light induced degradation could be improved by optimized rapid thermal processing (RTP). The important five different parameters varied in order to investigate which parameter is important for the stable lifetime after light induced degradation, $\tau_d$. The Plateau temperature and the Plateau time influenced on the lifetime after light induced degradation. Especially, the Plateau temperature showed a strong influence on the stable lifetime. The optimal plateau temperature is approximately $900^{\circ}C$ t for a plateau time of 120 s. The stable lifetime increased from $15\mu}s$ to $25.5{\mu}s$. The normalized defect concentration, $N_t^*$, decreased from $0.06{\mu}s^{-1}$ to $0.037{\mu}s^{-1}$ by RTP-process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.26-26
• /
• 2010

Cadmium sulfide (CdS) thin film for flexible optical device applications were prepared at $H_2(Ar+H_2)$ flow ratios on polyethersulfon(PES) flexible polymer substrates at room temperature by radio frequency magnetron sputtering technique. The CdS thin films deposited at room temperature showed a (002) preferred orientation and the smooth surface morphologies. Films deposited at a hydrogen flow ratio of 25% exhibited a photo- and dark-sheet resistance of about 50 and $2.7{\times}10^5{\Omega}$/square, respectively. From the result of the bending test, CdS films exhibit a strong adhesion with the PES polymer substrates and the $Al_2O_3$ passivation layer deposited on the CdS films only shows an increase of the resistance of 8.4% after exposure for 120 h in air atmosphere.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.11a
• /
• pp.163-163
• /
• 2008

반도체 소자가 고집적화 되고 고속화를 필요로 하게 됨에 따라, 기존에 사용되었던 알루미늄이나 텅스텐보다 낮은 전기저항, 높은 electro-migration resistance으로 미세한 금속배선 처리가 가능한 Cu가 주목받게 되었다. 하지만 과잉 디싱 현상과 에로젼을 유도하여 메탈라인 브리징과 단락을 초래할 있고 Cu의 단락인 islands를 남김으로서 표면 결함을 제거하는데 효과적이지 못다는 단점을 가지고 있었다. 특히 평탄화 공정시 높은 압력으로 인하여 Cu막의 하부인 ILD막의 다공성의 low-k 물질의 손상을 초래 할 수 있는 문제점을 해결하기 위하여 기존의 CMP에 전기화학을 결합시킴으로서 낮은 하력에서의 Cu 평탄화를 달성 할 수 있는 기존의 CMP 기술에 전기화학을 접목한 새로운 개념의 ECMP (electrochemical-mechanical polishing) 기술이 생겨나게 되었다. 따라서 본 논문에서는 최적화된 ECMP 공정을 위하여 I-V곡선과 CV법을 이용하여 active. passive. trans-passive 영역의 전기화학적 특징을 알아보았고. Cu막의 표면 형상을 알아보기 위해 Scanning Electron Microscopy (SEM) 측정과 Energy Dispersive Spectroscopy (EDS) 분석을 통해 금속 화학적 조성을 조사하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.11a
• /
• pp.115-116
• /
• 2008

The ferroelectric vinylidene fluoride-trifluoroethylene ($VF_2$-TrFE) and $Al_2O_3$ passivation layer for the Metal/Insulator/Ferroelectric/Semiconductor (MIFS) structure were deposited using spin coating and remote plasma atomic layer deposition (RPALD), respectively. A 2.5 ~ 3 wt % diluted solution of purified vinylidene fluoride-trifluoroethylene ($VF_2$: TrFE=70:30) in a DMF solution were prepared and deposited on silicon wafer at a optimized spin speed. After annealing in a vacuum ambient at 150 ~ $200^{\circ}C$ for 60 min, upper insulator layer were deposited at temperature ranging from 100 ~ $150^{\circ}C$ by RPALD. We described electrical and structural properties of MIFS fabricated by spin coating and RPALD methods.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.21 no.8
• /
• pp.687-694
• /
• 2008

This paper is focused on the improvement of MOS device reliability related to deuterium process. The injection of deuterium into the gate oxide film was achieved through two kind of method, high-pressure annealing and low-energy implantation at the back-end of line, for the purpose of the passivation of dangling bonds at $SiO_2/Si$ interface. Experimental results are presented for the degradation of 3-nm-thick gate oxide ($SiO_2$) under both negative-bias temperature instability (NBTI) and hot-carrier injection (HCI) stresses using P and NMOSFETs. Annealing process was rather difficult to control the concentration of deuterium. Because when the concentration of deuterium is redundant in gate oxide excess traps are generated and degrades the performance, we found annealing process did not show the improved characteristics in device reliability, compared to conventional process. However, deuterium ion implantation at the back-end process was effective method for the fabrication of the deuterated gate oxide. Device parameter variations under the electrical stresses depend on the deuterium concentration and are improved by low-energy deuterium implantation, compared to conventional process. Our result suggests the novel method to incorporate deuterium in the MOS structure for the reliability.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.18 no.6
• /
• pp.515-520
• /
• 2005

CMP(chemical mechanical polishing) process has been attracted as an essential technology of multi-level interconnection. Also CMP process got into key process for global planarization in the chip manufacturing process. In this study, potentiodynamic polarization was carried out to investigate the influences of $H_2O_2$ concentration and metal oxide formation through the passivation on tungsten and titanium. Fortunately, the electrochemical behaviors of tungsten and titanium are similar, an one may expect. As an experimental result, electrochemical corrosion of the $5\;vol\%\;H_2O_2$ concentration of tungsten and titanium films was higher than the other concentrations. According to the analysis, the oxidation state and microstructure of surface layer were strongly influenced by different oxidizer concentration. Moreover, the oxidation kinetics and resulting chemical state of oxide layer played critical roles in determining the overall CMP performance. Therefore, we conclude that the CMP characteristics tungsten and titanium metal layer including surface roughness were strongly dependent on the amounts of hydrogen peroxide oxidizer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1988.05a
• /
• pp.78-81
• /
• 1988

Nitroxide films were made from the $NH_3$ gas nitridation of as-grown $SiO_2$. The electrical characterization results including C-V characteristics and BT stress generally indicate that the high field stress instability and insulator-substrate interfacial characteristics are improved by nitridation of $SiO_2$. A C-V technique was used to determine the surface state density $N_{55}$ and then $N_{55}$ in the nitroxide-substrate interface was $8{\times}10(/eVcm^2$). This $N_{55}$ is related with 1/f noise was revealed experimentally and relationship was plotted and 1/f noise characteristics were also improved by nitridation of of $SiO_2$By the results of measurements on these films show that very thin thermal silicon nitroxide films can be used as gate dielectrics for future highly scaled-down VLSI device.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.6
• /
• pp.471-476
• /
• 2003

Au/oxide/n-InP Schottky diodes were fabricated from heteroepitaxial InP layers grown on GaAs substrates by the metalorganic vapor phase epitaxy (MOVPE) method from a new combination of source materials: ethyldimethylindium (EDMIn) and tertiarybutylphosphine (TBP). Anodic oxidation technique by using a solution of 10 g of ammonium pentaborate in 100 cc of ethylene glycole as the electrolyte was used to deposit a thin oxide layer. The barrier heights determined from three different techniques, current-voltage (I-V) measurements at room temperature and in the temperature range of 273 K - 373 K, and room temperature capacitance-voltage (C-V) measurements are in good agreement, 0.7 - 0.9 eV which is considerably high as compared to the 0.45 - 0.55 eV in Au/n-InP Schottky diode without a Passivation layer. The ideality factors of 1.1 - 1.3 of the Schottky diodes were also determined from the I-Y characteristics. Deep level transient spectroscopy (DLTS) studies revealed only one shallow electron state at 92.6 meV below the bottom of the conduction band and no deep state in the heteroepitaxial InP layers grown from EDMIn and TBP.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.15 no.12
• /
• pp.1016-1020
• /
• 2002

Ru thin films were etched using CF/$_4$O$_2$ plasma in an ICP (inductively coupled plasma etching) system. The maximum etch rate of Ru thin films was 168 nm/min at a CF$_4$/O$_2$ gas mixing ratio of 10 %. The selectivity of SiO$_2$ over Ru was 1.3. From the OES (optical emission spectroscopy) analysis, the optical emission intensity of the O radical had a maximum value at 10% CF$_4$ gas concentration and drcrease with further addition of CF4 gas, but etch slope was enhanced. From XPS (x-ray photoelectron spectroscopy) analysis, the surface of the etched Ru thin film in CF$_4$/O$_2$ chemistry shows Ru-F bonds by the chemical reaction of Ru and F. RuF$_{x}$ compounds were suggested as a surface passivation layer that reduces the chemical reactions between Ru and O radicals. From a FE-SEM (field emission scanning electron microscope) micrograph, we had an almost perpendicular taper angle of 89$^{\circ}$.>.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.112-112
• /
• 2008

최근 Ruthenium (Ru) 은 높은 화학적 안정성, 누설전류에 대한 높은 저항성, 저유전체와의 높은 안정성 등과 같은 특성으로 인해 금속층-유전막-금속층 캐패시터의 하부전극으로 각광받고 있다. 또한 Cu와의 우수한 Adhesion 특성으로 인해 Cu 배선에서의 Cu 확산 방지막으로도 주목받고 있다. 그러나 이렇게 형성된 Ru 하부전극의 각 캐패시터간의 분리와 평탄화를 위해서는 CMP 공정이 도입이 필요하다. 이러한 CMP 공정에 공급되는 Slurry 에는 부식액, pH 적정제, 연마입자 등이 첨가되는데 이때 연마입자가 응집하여 Slurry의 분산 안전성 저하에 영향을 줄수 있다. 이로 인해 응집된 Slurry는 Scratch와 Delamination 과 같은 표면 결함을 유발할 수 있으며, Slurry의 저장 안정성을 저하시켜 Slurry의 물리적 화학적 특성을 변화시킬 수 있다. 그리하여 본 연구에서는 Ru CMP Slurry에서의 Surfactant와 같은 분산 안정제에 따른 Surface tension, Zeta potential, Particle size, Sedimentation의 분석을 통해 Slurry 안정성에 대한 영향을 살펴보았다. 그 결과 pH9 조건의 31ppm Dispersant 농도에서 50%이상의 Sedimentation 상승효과를 얻을 수 있었다. 또한 선택된 Surfactant가 첨가된 Ru CMP Slurry를 제조하여 Ru wafer의 Static etch rate, Passivation film thickness 와 Wettability를 비교해 보았다. 그리고 CMP 공정을 실시하여 Ru의 Removal rate와 TEOS에대한 Selectivity를 측정해 보았다.