• 한국항행학회논문지
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• 제13권5호
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• pp.684-690
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• 2009

본 논문에서는 차세대 스토리지 시스템의 디스크 시스템인 DDR-SSD를 이용하여 RAID 레벨 5를 구성하였을 때 고속화 방법을 제안한다. DDR-SSD는 HDD와 Flash SSD와는 다른 특성을 가지고 있기 때문에 기존의 고속화 기법으로는 최상의 성능을 보이지 못한다. 본 논문에서는 고속화를 위해 패리티 정보만 저장하는 패리티 캐시를 사용하는 것과 패리티 캐시의 저장 셀인 패리티 셀의 구조를 제안하였다. 이것은 디스크 접근 횟수의 감소보다는 패리티 연산 오버헤드를 감소시킨다.

• 한국통신학회논문지
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• 제31권11C호
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• pp.1030-1036
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• 2006

In this paper, we present two methods of correcting bit errors in constant amplitude multi-code (CAMC) CDMA, which uses the redundant bits only. The first method is a parity-based bit correction with hard-decision, where the received signals despread into n two-dimensional structure with both horizontal parity and vertical parity. Then, an erroneous bit is corrected for each $4{\times}4$ pattern. The second method is a turbo decoding, which is modified from the decoding of a single parity check product code (SPCPC). Experimental results show that, in the second method, the redundant bits in CAMC can be fully used for the error correction and so they are not really a loss of channel bandwidth. Hence, CAMC provides both a low peak-to-average power ratio and robustness to bit errors.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 추계학술대회
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• pp.107-108
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• 2012

분산 비디오 부호화기(DVC)에서 패리티 비트를 채널을 통해 전송하는 기법은 초경량 비디오 압축 기술의 핵심적인 부분이다. 하지만 복호과정 중 피드백 채널을 이용하여 패리티 비트 전송량을 제어하는 방법이 주로 사용되기 때문에 복호 시간 증가의 원인이 되고 있다. 본 논문에서는 고속 분산 비디오 복호화를 위해 패리티 비트 요구량을 움직임 정보 피드백을 이용하여 예측하는 기법을 제안한다. 먼저 율-왜곡에 대한 모델을 제시하고, 시간적인 상관성이 높은 영상의 특성을 이용하여 이전 프레임의 LDPCA 프레임의 패리티 비트 요구량에 모델을 적용하는 방법을 제안한다.

• 에너지공학
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• 제17권4호
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• pp.233-240
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• 2008

최근 새로운 2계 자기 수반형(self-adjoint) 중성자 수송 방정식으로 기존의 우성 및 기성 수송 방정식 외에 SAAF(Self-Adjoint Angular Flux) 수송 방정식이 소개되어, 이에 대한 적절한 경계조건, 수치해법, 정확도 등에 관한 논의가 활발히 진행되고 있다. 본 연구에서는 SAAF 수송 방정식의 수학적, 물리적 의미를 고찰하고 기존의 우성 및 기성 수송 방정식과의 연관성을 명확히 하였으며, Boltzmann 수송 방정식의 1계 차분식에서 2계의 SAAF 수송 방정식의 차분식을 유도하는 방법을 확산 가속법(diffusion synthetic acceleration method)과 함께 소개하였다. 유도된 SAAF 차분법이 계산 효율성과 수송해의 정확도를 증가시킴을 수치결과로 확인하였다.

• 한국가축번식학회지
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• 제10권1호
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• pp.83-90
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• 1986

This study was conducted to determine the main effects of year, month, sire and parity on certain reproduction and lactation traits on the basis of the data obtained from 1,510 head of Holstein cows at National Animal Breeding Institute from 1971 to 1981. The results obtained in this study are summarized as follows; 1. The conception interval and number of services per concetption were 124.10 days and 2.19 times, respectively. The effects of year, month and sire on the above traits were significant. 2. The birth weight and gestation length were 42.20kg and 281.52 days, respectively. The effects of year, month and parity on the birth weight, and year, sire and parity on gestation length were significant. 3. The yields of milk and milk fat in 305 days, and the fat percent were 4937.05kg, 174.43kg and 3.56%, respectively. The effects of year, month, sire and parity on the above traits were significant. 4. The peak yield and days reaching the peak yield were 26.46kg and 49.17 days, respectively. The effects of the sire and parity on above traits were significant.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.2188-2191
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• 2005

We consider a fault detection and isolation problem for inertial navigation systems which use redundant inertial sensors. We propose a FDI method using average of multiple parity vectors which reduce false alarm and wrong isolation, and improve correct isolation. We suggest the number of redundant sensors required to isolate simultaneous faults. The performance of the proposed FDI algorithm is analyzed by Monte-Carlo simulation.

• 한국산업정보학회:학술대회논문집
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• 한국산업정보학회 1997년도 추계학술대회 발표논문집:21세기를 향한 정보통신 기술의 전망
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• pp.137-146
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• 1997

The simplest bit error detection scheme is to append a parity bit to the end of a bit sequence. In this paper an error correction technique with the use of a parity bit is proposed, and the performance of the proposed system is analyzed. The error probability of the proposed system is compared with the output of computer simulation of the proposed system. It is also compared with the error probability of error at BPSK system, and the signal-to-noise ratio gain is showed.

• 한국통신학회논문지
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• 제35권6B호
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• pp.984-990
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• 2010

In Current Digital $C^3$ Devices(Communication, Computer, Consumer electronic devices), Reed-Solomon encoder is essentially used. For example we should use RS encoder in DSP LSI of CDMA Mobile and Base station modem, in controller LSI of DVD Recorder and that of computer memory(HDD or SSD memory). In this paper, we propose new economical multiplierless (also without divider) RS encoder design method. The encoder has Arbitrary parity positions.

• East Asian Economic Review
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• 제22권4호
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• pp.467-505
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• 2018

We propose a simple identification scheme for the causes of the violations of uncovered interest parity. Our method uses the serial dependence patterns of excess returns as a criterion for judging performance of economic models. We show that a mean reverting component in excess returns, representing a violation of uncovered interest parity, mainly contributes to generating different serial dependence patterns of excess returns: rational expectations risk premium models tend to generate negative serial dependence of excess returns, while expectational errors models tend to generate positive serial dependence.

• ETRI Journal
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• 제27권5호
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• pp.557-562
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• 2005

Low-density parity-check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and are synthesized using a $0.35 {\mu}m$ CMOS standard cell library.