• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.8
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• pp.114-120
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• 2008

In this paper, we extract the parasitic elements of the metal-insulate-metal(MIM) capacitor using short-open calibration (SOC). The scattering matrixes of short, open, and MIM structures in strip lines are measured by full electro-magnetic (EM) simulator and vector network analyser. The full EM simulations are performed by finite element method (FEM) that was fitted three dimensional structure analysis. The electro-magnetic effects of MIM capacitor laminated in the multi-layered structures are proposed the II equivalent circuit with lumped elements, and the relations between the measured scattering parameters of the MIM structures and lumped elements in the circuits are shown by performing 2 port network analysis. The extracted lumped elements using the proposed SOC method are independent to frequencies.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.33-46
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• 2015

In this paper, we predicts the analog and digital circuit performance of FinFETs that are scaled down following the ITRS(International technology roadmap for semiconductors). For accurate prediction of the circuit performance of scaled down devices, accurate parasitic resistance and capacitance analytical models are developed and their accuracies are within 2 % compared to 3D TCAD simulation results. The parasitic capacitance models are developed using conformal mapping, and the parasitic resistance models are enhanced to include the fin extension length($L_{ext}$) with respect to the default parasitic resistance model of BSIM-CMG. A new algorithm is developed to fit the DC characteristics of BSIM-CMG to the reference DC data. The proposed capacitance and resistance models are implemented inside BSIM-CMG to replace the default parasitic model, and SPICE simulations are performed to predict circuit performances such as $f_T$, $f_{MAX}$, ring oscillators and common source amplifier. Using the proposed parasitic capacitance and resistance model, the device and circuit performances are quantitatively predicted down to 5 nm FinFET transistors. As the FinFET technology scales, due to the improvement in both DC characteristics and the parasitic elements, the circuit performance will improve.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.11 s.114
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• pp.1082-1088
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• 2006

A turnstile antenna using the parasitic monopole has been developed for STSAT-2 TT&C application. The antenna consists of two radiating elements; a bow-tie dipole and a parasitic monopole. The bow-tie dipole is main radiating element, used a bow-tie structure for bandwidth improvement and size reduction. The parasitic monopole improved beamwidth and axial ratio. The input impedance of the antenna is about 50 ohm without a matching circuit. The proposed antenna has beamwidth of $>140^{\circ}$, axial ratio of < 3 dB and VSWR of < 1.5 in the band of $2.075{\sim}2.282GHz$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.7
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• pp.737-746
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• 2014

Recently, researches about MIMO(Multi-Input Multi-Output) system are being studied actively due to high-capacity and high-speed communication. However, MIMO system has many RF(Radio Frequency) chains according to many array antennas. So, MIMO system has disadvantages such as high-complexity and high-power-consumption. Also, it is impossible to miniaturize the antenna dimension. In order to solve these problems, beamspace MIMO system using ESPAR(Electronically Steerable Parasitic Array Radiator) antenna was proposed. It is possible to reduce the complexity and the power-consumption, because it has single RF chain by using one active antenna and several parasitic elements. In this paper, in order to improve the security, for the first time, chaos communication algorithm is applied to QPSK modulated beamspace MIMO system using ESPAR antenna. We define as chaos QPSK beamspace MIMO system, and evaluate the SER performance. Also, we confirm that QPSK symbols can be made by changing the reactance values of parasitic elements, and evaluate the SER performance of this system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2655-2661
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• 2009

In this paper, an accurate noise parameters for thermal noise modeling of short channel MOSFET is derived and extracted. Fukui model for calculating the noise parameters of a MOSFET is modified by considering effects of parasitic elements in short channel, and it is compared with conventional noise model equation. In addition, for obtaining the intrinsic noise sources of devices, noise parameters(minimum noise figure $F_{min}$, equivalent noise resistance $R_n$ optimized source admittance $Y_{opt}=G_{opt}+B_{opt}$) in submicron MOSFETs is extracted. With this extraction method, the intrinsic noise parameters of MOSFET without effects of probe pad and extrinsic parasitic elements from RF noise measurements can be directly obtained.

• Journal of international Conference on Electrical Machines and Systems
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• v.2 no.1
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• pp.57-64
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• 2013

The functional characteristic of LISN circuit, which is used for measurements of conductive noise in mains power line, is basically related to frequency characteristics of passive elements like inductors used in the circuit as well as the frequency response of inductors is highly related to the resins used in the varnishing process. The significant problem in determination of an inductor's frequency characteristic is the intrinsic resistance, inductance and parasitic capacitance. In this triplet, the parasitic capacitance is the major limiting factor of inductor's frequency range. This capacitance depends on inductor design parameters and materials filling the spaces of coil like resin and its coherency after curing process. In this paper, two similar inductors were designed and built. The first inductor was not varnished while the second one was varnished with VPI technology. VPI, or Vacuum, Pressure, Impregnation technology is one of the most reliable methods performing good insulating conditions for electrical circuits and windings based on resins. The measured results show that implying varnishing technology does not significantly affect the frequency response. However, due to mechanical solidity aspects and improved environmental protection, it is better to varnish the inductors.

• Journal of electromagnetic engineering and science
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• v.1 no.1
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• pp.37-42
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• 2001

This paper presents the basic characteristics of a cutoff cavity-hacked slot antenna, for the application of spacetenna, with a feed post and a parasitic post inserted parallel to the slot. This type of antenna might effectively excite the slot and forcibly resonate the cavity by adding external reactance to the parasitic post. The Galerkin\`s method of moments is used to analyze integral equations for the unknown electric current on each post and electric field in the slot. The value of external reactance for forced resonance is discussed by deriving a determining equation, the current distribution on each post and the radiation patterns are considered. The analysis is in excellent agreement with the experiment for the radiation patterns.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.821-823
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• 2015

In this paper, we investigate the SPA(Switched Parasitic Antenna), which is novel method of electronic beam steering. We analyzed the performance of the monopole SPA with one central active element surrounded by 4 parasitic elements. And we evaluate the performance of a wireless LAN using SPA antenna beamforming.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.4
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• pp.672-678
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• 1994

A design of 5th-order Elliptic OTA-C filter for operation at 4.2MHz is presented. the filter structure is composed entirely of five OTAs(Operational transoonductance Amplifiers), one buffer and seven capacitors. To prevent decreasing of frequency charaoteristios due to the parasitic effeots of OTA and buffer, the design considering of parasitic capacitance and finite resistane of OTA and fuffer is pertormed. As the result of the simulation using SPICE with $2{\mu}m$ CMOS parameters, The performances were found to be essentially within the specifications` less than 0.25dB passband attenuation, 30dB stopband attenuation and 4.2MHz cut-off frequency were satisfactorily obtained. The number of elements is also considerably reduced than other design methods.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.4
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• pp.71-78
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• 2005

This paper proposes a novel multi-level energy recovery sustaining driver for AC PDP(Plasma Display Panel), which solves the problems of the conventional multi-level sustaining driver. While the conventional circuit improves the voltage md current stress of the switching elements in Weber circuit not only there are parasitic resonant currents between resonant inductors and parasitic capacitance and hard switching, but also the changing period between 0 and sustain voltage is too long. Comparing the proposed circuit with the conventional circuit, the number of components are reduced and the parasitic resonant currents in resonant inductors are eliminated Moreover the hard switching problem is solved by using CIM(Current Injection Method) and the operating frequency will be high as much as possible by removing Vs/2 sustain period. And the circuit operations of the proposed circuit are analyzed for each mode and the validity is verified by the simulations using PSpice program.