• 제목/요약/키워드: Parallel-mesh circuit

검색결과 5건 처리시간 0.018초

원형 Cavity를 이용한 펄스형 Nd:YAG레이저의 출력특성 및 병렬메쉬 회로의 최적화 (The Output Characteristics and the Optimization of Parallel-mesh Circuit of a Pulsed Nd:YAG Laser by Using a Circular Cavity)

  • 홍정환;양동민;김병균;박구렬;강욱;김휘영;김희제
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1999년도 하계학술대회 논문집 E
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    • pp.2201-2203
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    • 1999
  • In this study, we have designed and manufactured not a present elliptic cavity but a circular cavity and we have experimented the operational characteristics. As a result, we obtained the maximum efficiency of 2.1 %. It didn't have any difference compared with elliptic cavity. A circular cavity is much more compact, so far easier to be manufactured than a elliptic cavity. And it can be made at a low cost. At the input energy, parameter $\alpha$, input voltage, and pulse width were in the same condition, we have decided to the optimization of the mesh number of a parallel-mesh circuit which was connected with main power supply.

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재구성 가능한 메쉬에서 결정적 유한 자동장치 문제에 대한 상수시간 알고리즘 (A Constant Time Algorithm for Deterministic Finite Automata Problem on a Reconfigurable Mesh)

  • 김영학
    • 한국정보처리학회논문지
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    • 제6권11호
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    • pp.2946-2953
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    • 1999
  • Finite automation is a mathematical model to represent a system with discrete inputs and outputs. Finite automata are a useful tool for solving problems such as text editor, lexical analyzer, and switching circuit. In this paper, given a deterministic finite automaton of an input string of length n and m states, we propose a constant time parallel algorithm that represents the transition states of finite automata and determines the acceptance of an input string on a reconfigurable mesh of size [nm/2]$\times$2m.

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SliM 이미지 프로세서 칩 설계 및 구현 (Design and implementation of the SliM image processor chip)

  • 옹수환;선우명훈
    • 전자공학회논문지A
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    • 제33A권10호
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    • pp.186-194
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    • 1996
  • The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

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3단 병렬 충.방전 방식을 적용한 고반복 펄스형 Nd:YAG 레이저 출력거울 반사율의 최적화 (The optimization of output coupler reflectivity of high repetitive pulsed Nd:YAG laser system adopted 3-mesh parallel sequential charge and discharge method)

  • 김휘영;홍수열;김동수
    • 한국컴퓨터산업학회논문지
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    • 제2권3호
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    • pp.369-376
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    • 2001
  • 펄스형 YAG 레이저 시스템의 효율개선을 위해서는 공진기 및 레이저 전원장치의 최적화가 필수적이다. 따라서, 본 연구에서는 공진기 출력거울의 반사율 최적화 및 기존의 전원보다 훨씬 컴팩하고, 경제적이며 가공목적에 따라 출력을 정밀하게 제어할 수 있는 새로운 방식의 레이저시스템을 설계 및 제작하였다. 그 결과 50[W]급의 펄스형 Nd:YAG 레이저 시스템에서는 출력거울의 반사율이 85%일 때 최대 출력을 나타내었다. 그리고 3단 병렬 충ㆍ방전 방식의 전원시스템은 3개의 콘덴서가 순차적으로 충ㆍ방전함으로서 1개의 콘덴가 충ㆍ방전하는 방식보다 더 많은 에너지를 플래쉬램프에 전달할 수 있어 더 높은 출력을 얻을 수가 있었다. 실험을 통해 제시한 방법의 타당성을 검증하였다.

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일반화된 Hough 변환을 위한 특수 목적 VLSI 시스템 설계에 관한 연구 (Specialized VLSI System Design for the Generalized Hough Transform)

  • 채옥삼;이정헌
    • 전자공학회논문지B
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    • 제32B권3호
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    • pp.66-76
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    • 1995
  • In this research, a mesh connected VLSI structure is proposed for the real time computation of the generalized Hough transform(GHT). The purpose of the research is to design a generalized Hough transformer that can be realized as a single chip processor. The GHT has been modified to yield a highly parallel structure consisting of simple processing elements(PEs) and communication networks. In the proposed structure, the GHT can be computed by first assigning an image pixel to a PE and performing shift and add operations. The result of the CAD circuit simulation shows that it can be computed in the time proportional to the number of pixels in the pattern. In addition to the Hough transformer, the peak detector has been designed to reduce 1)the number of the I/O operations between the transformer and the host computer and 2) the host computer's burden for peak detection by transmitting only the local peaks detected from the transformed accumulator. It is expected that the proposed single chip Hough transformer with peak detector makes a fast and inexpensive edge based object recognition systems possible for many industrial and military applications.

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