• Proceedings of the KIEE Conference
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• 1999.07e
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• pp.2201-2203
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• 1999

In this study, we have designed and manufactured not a present elliptic cavity but a circular cavity and we have experimented the operational characteristics. As a result, we obtained the maximum efficiency of 2.1 %. It didn't have any difference compared with elliptic cavity. A circular cavity is much more compact, so far easier to be manufactured than a elliptic cavity. And it can be made at a low cost. At the input energy, parameter $\alpha$, input voltage, and pulse width were in the same condition, we have decided to the optimization of the mesh number of a parallel-mesh circuit which was connected with main power supply.

• The Transactions of the Korea Information Processing Society
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• v.6 no.11
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• pp.2946-2953
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• 1999

Finite automation is a mathematical model to represent a system with discrete inputs and outputs. Finite automata are a useful tool for solving problems such as text editor, lexical analyzer, and switching circuit. In this paper, given a deterministic finite automaton of an input string of length n and m states, we propose a constant time parallel algorithm that represents the transition states of finite automata and determines the acceptance of an input string on a reconfigurable mesh of size [nm/2]$\times$2m.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.186-194
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• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

• Journal of the Korea Computer Industry Society
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• v.2 no.3
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• pp.369-376
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• 2001

The optimization of resonator and laser power supply has been considered to be significant for improving the efficiency of a pulsed Nd:YAG laser system. We have proposed a new method of 3-mesh parallel sequential charge and discharge circuit as a laser power supply; more compact than conventional power supply, competitive in price, easy to control the laser power density according to various material processing, and equipped with the optimum reflectivity of output coupler. In this study, we could find that the maximum laser output was obtained by using 85% of reflectivity in the case of 50[W]-class. In addition using the power supply of new method, it's possible to charge each capacitor bank with a higher energy within the given charging time adopted a new method mentioned above; namely, we can allow each capacitor to have much more charging time and storage energy. So, higher laser output was obtained than conventional power supply.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.3
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• pp.66-76
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• 1995

In this research, a mesh connected VLSI structure is proposed for the real time computation of the generalized Hough transform(GHT). The purpose of the research is to design a generalized Hough transformer that can be realized as a single chip processor. The GHT has been modified to yield a highly parallel structure consisting of simple processing elements(PEs) and communication networks. In the proposed structure, the GHT can be computed by first assigning an image pixel to a PE and performing shift and add operations. The result of the CAD circuit simulation shows that it can be computed in the time proportional to the number of pixels in the pattern. In addition to the Hough transformer, the peak detector has been designed to reduce 1)the number of the I/O operations between the transformer and the host computer and 2) the host computer's burden for peak detection by transmitting only the local peaks detected from the transformed accumulator. It is expected that the proposed single chip Hough transformer with peak detector makes a fast and inexpensive edge based object recognition systems possible for many industrial and military applications.