• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.4
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• pp.336-344
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• 2017

This paper presents the three-port DC-DC converter modeling and controller design procedure, which is part of the solid-state transformer (SST) to interface medium voltage AC grid to bipolar DC distribution network. Due to the high primary side DC link voltage, the proposed converter employs the three-level neutral point clamped (NPC) topology at the primary side and 2-two level half bridge circuits for each DC distribution network. For the proposed converter particular structure, this paper conducts modeling the three winding transformer and the power transfer between each port. A decoupling method is adopted to simplify the power transfer model. The voltage controller design procedure is presented. In addition, the output current sharing controller is employed for current balancing between the parallel-connected secondary output ports. The proposed circuit and controller performance are verified by experimental results using a 30 kW prototype SST system.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.54 no.1
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• pp.33-39
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• 2005

Comparing with the conventional transformer without the air gap, a contactless transformer with the large air gap between the long primary winding and the secondary winding has increased leakage inductance and reduced magnetizing inductance. For transferring the primary power to the secondary one, the high frequency series resonant converter has been widely used for the contactless power supply system with the large air gap and the increased leakage inductance of the contactless transformer However, the high frequency series resonant converter has the disadvantages of the low efficiency and high voltage gain characteristics in the overall load range due to the large air gap and the circulating magnetizing current. In this paper, the characteristics of the high efficiency and unit voltage gain are revealed in the proposed three-level series-parallel resonant converter. The results are verified on the simulation based on the theoretical analysis and the 5kW experimental prototype.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.974-977
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• 1999

In this paper, we have proposed the hardware architecture which implements the algorithm for retaining the connectivity which prevents disconnecting in the gray-scale image thinning To perform the image thinning in a real time which find a skeleton in image, it is necessary to examine the connectivity of the skeleton in a real time. The proposed architecture finds the connectivity number in the 4-clock period. The architecture is consists of three blocks, PS(Parallel to Serial) Converter and State Generator and Ridge Checker. The PS Converter changes the 3$\times$3 gray level image to four sets of image pixels. The State Generator examine the connectivity of the central pixel by searching the data from the PS Converter. the 3$\times$3 gray level image determines. The Ridge Checker determines whether the central pixel is on the skeleton or not The proposed architecture finds the connectivity of the central pixel in a 3$\times$3 gray level image in the 4-clocks. The total circuits are verified by the design tools and operate correctly.

• Proceedings of the KIEE Conference
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• summer
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• pp.1166-1168
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• 2004

The high frequency series resonant converter has been widely used for the non-contact power supply system with the large air gap and the increased leakage inductance of the non-contact transformer. However. the high frequency series resonant converter has the disadvantages of high voltage gain characteristics in the overall load range due to the large air gap and the circulating magnetizing current. In this paper, unit voltage gain is revealed in the proposed three-level series-parallel resonant converter. The results are verified on the simulation results and the 5kW experimental prototype.

• Journal of the Institute of Convergence Signal Processing
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• v.3 no.4
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• pp.23-28
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• 2002

In this paper, we have proposed the hardware architecture which implements the algorithm for retaining the connectivity which prevents the disconnection in the gray-scale image thinning. To extract the skeleton from the image in a real time, it is necessary to examine the connectivity of the skeleton in a real time. The proposed architecture finds the connectivity number in the 4-clock period. The architecture consists of three blocks, PS(Parallel to Serial) Converter and Stare Generator and Ridge Checker. The PS Converter changes the 3$\times$3 gray level image to four sets of image pixels. The State Generator examines the connectivity of the central pixel by searching the data from the PS Converter. The Ridge Checker determines whether the central pixel is on the skeleton or not. The proposed architecture finds the connectivity of the central pixel in a 3$\times$3 gray level image in the 4-clocks. The total circuits are verified by the design tools and operate correctly.

• Journal of Power Electronics
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• v.13 no.1
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• pp.20-30
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• 2013

This paper presents a soft switching DC/DC converter for high voltage application. The interleaved pulse-width modulation (PWM) scheme is used to reduce the ripple current at the output capacitor and the size of output inductors. Two converter cells are connected in series at the high voltage side to reduce the voltage stresses of the active switches. Thus, the voltage stress of each switch is clamped at one half of the input voltage. On the other hand, the output sides of two converter cells are connected in parallel to achieve the load current sharing and reduce the current stress of output inductors. In each converter cell, a half-bridge converter with the asymmetrical PWM scheme is adopted to control power switches and to regulate the output voltage at a desired voltage level. Based on the resonant behavior by the output capacitance of power switches and the transformer leakage inductance, active switches can be turned on at zero voltage switching (ZVS) during the transition interval. Thus, the switching losses of power MOSFETs are reduced. The current doubler rectifier is used at the secondary side to partially cancel ripple current. Therefore, the root-mean-square (rms) current at output capacitor is reduced. The proposed converter can be applied for high input voltage applications such as a three-phase 380V utility system. Finally, experiments based on a laboratory prototype with 960W (24V/40A) rated power are provided to demonstrate the performance of proposed converter.

• Journal of Power Electronics
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• v.13 no.5
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• pp.877-883
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• 2013

This paper discussed a transformer-less shunt static synchronous compensator (STATCOM) with consideration of the following aspects: fast compensation of the reactive power, harmonic cancelation and reducing the unbalancing of the 3-phase source side currents. The STATCOM control algorithm is based on the theory of instantaneous reactive power (P-Q theory). A self charging technique is proposed to regulate the dc capacitor voltage at a desired level with the use of a PI controller. In order to regulate the DC link voltage, an off-line Genetic Algorithm (GA) is used to tune the coefficients of the PI controller. This algorithm arranged these coefficients while considering the importance of three factors in the DC link voltage response: overshoot, settling time and rising time. For this investigation, the entire system including the STATCOM, network, harmonics and unbalancing load are simulated in MATLAB/SIMULINK. After that, a 35KVA STATCOM laboratory setup test including two parallel converter modules is designed and the control algorithm is executed on a TMS320F2812 controller platform.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.12
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• pp.1923-1930
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• 2004

This paper presents digital microflow controllers(DMFC), where a fluidic digital-to-analog converter(DAC) is used to achieve high-linearity, fine-level flow control for applications to precision biomedical dosing systems. The fluidic DAC, composed of binary-weighted flow resistance, controls the flow-rate based on the ratio of the flow resistance to achieve high-precision flow-rate control. The binary-weighted flow resistance has been specified by a serial or a parallel connection of an identical flow resistor to improve the linearity of the flow-rate control, thereby making the flow-resistance ratio insensitive to the size uncertainty in flow resistors due to micromachining errors. We have designed and fabricated three different types of 4-digit DMFC: Prototype S and P are composed of the serial and the parallel combinations of an identical flow resistor, while Prototype V is based on the width-varied flow resistors. In the experimental study, we perform a static test for DMFC at the forward and backward flow conditions as well as a dynamic tests at pulsating flow conditions. The fabricated DMFC shows the nonlinearity of 5.0% and the flow-rate levels of 16(2$^{N}$) for the digital control of 4(N) valves. Among the 4-digit DMFC fabricated with micromachining errors, Prototypes S and P show 27.2% and 27.6% of the flow-rate deviation measured from Prototype V, respectively; thus verifying that Prototypes S and P are less sensitive to the micromachining error than Prototype V.V.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.434-435
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• 2010

본 논문에서는 배전급 고전압(1kV~7.2kV) 계통 연계가 가능한 새로운 3 병렬 3 레벨 NPC(Neutral-Point-Clamped) 컨버터/인버터 회로방식을 제안한다. 이 회로방식은 정격 용량의 1/3 크기를 가지는 NPC 컨버터/인버터 모듈을 3 병렬로 구성하면서 직류단 캐패시터를 병렬 연결하여 중성점 전위 변동을 저감할 수 있는 특징을 가진다. 제안된 3 병렬 3 레벨 NPC 컨버터/인버터는 기존의 NPC 컨버터의 장점을 가지면서 동시에 용량 확장이 가능하고, 하나의 모듈이 고장 상태가 되더라도 부분 운전이 가능하여 시스템의 신뢰성을 증대시킬 수 있다. 본 논문에서는 제안된 중성점 전압 제어 전략을 실험을 통하여 검증한다. 정밀한 중성점 전압 제어를 위한 중성점 전류 제어 방법이 3병렬 구조에서 안정적으로 동작함을 컴퓨터 모의 실험을 통해 검증한다.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.391-392
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• 2020

본 논문은 3레벨 정류기와 직렬 입력, 병렬 출력 LLC 컨버터가 연결된 전원 장치의 DC-Link 전압 불평형 제어에 관해 분석한다. 일반적으로 380Vac 입력을 가지는 3레벨 부스트 기반 정류기는 출력 전압을 700Vdc 이상으로 제어한다. 또한, 3레벨 컨버터는 두 개의 직렬 출력 커패시터를 가지며, 불균형 해소를 위한 제어 또는 물리적 불평형 해소 소자가 요구된다. 스위칭 신호를 공유하는 두 개의 LLC 컨버터가 연결된 시스템에 DC-Link 불평형 전압 제어가 적용되면 전력의 쏠림 현상이 발생한다. 본 논문은 제시된 시스템에서 전력의 쏠림 현상에 대해 그 원인을 분석하고 실험으로 검증한다.