• Title/Summary/Keyword: Parallel process

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Delayed Parallel Interference Cancellation for GPS C/A Code Receivers

  • Glennon, Eamonn P.;Bryant, Roderick C.;Dempster, Andrew G.
    • Proceedings of the Korean Institute of Navigation and Port Research Conference
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    • v.2
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    • pp.261-266
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    • 2006
  • A number of different techniques are available to mitigate the problem of cross correlations caused by the limited dynamic range of the 10-bit Gold codes in the GPS C/A code. These techniques include successive-interference cancellation (SIC) and parallel-interference cancellation (PIC), where the strong signals are subtracted at IF prior to attempting to detect the weak signals. In this paper, a variation of these techniques is proposed whereby the subtraction process is delayed until after the correlation process, although still employing a pure reconstructed C/A code signal to permit prediction of the cross correlation process. The paper provides details on the method as well as showing the results obtained when the method was implemented using a software GPS receiver. The benefits of this approach are also described, as is the application of the method to the cancellation of CW interference.

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Design and Implementation of Real-Time Parallel Engine for Discrete Event Wargame Simulation (이산사건 워게임 시뮬레이션을 위한 실시간 병렬 엔진의 설계 및 구현)

  • Kim, Jin-Soo;Kim, Dae-Seog;Kim, Jung-Guk;Ryu, Keun-Ho
    • The KIPS Transactions:PartA
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    • v.10A no.2
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    • pp.111-122
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    • 2003
  • Military wargame simulation models must support the HLA in order to facilitate interoperability with other simulations, and using parallel simulation engines offer efficiency in reducing system overhead generated by propelling interoperability. However, legacy military simulation model engines process events using sequential event-driven method. This is due to problems generated by parallel processing such as synchronous reference to global data domains. Additionally. using legacy simulation platforms result in insufficient utilization of multiple CPUs even if a multiple CPU system is under use. Therefore, in this paper, we propose conversing the simulation engine to an object model-based parallel simulation engine to ensure military wargame model's improved system processing capability, synchronous reference to global data domains, external simulation time processing, and the sequence of parallel-processed events during a crash recovery. The converted parallel simulation engine is designed and implemented to enable parallel execution on a multiple CPU system (SMP).

Onboard CO2 Capture Process Design using Rigorous Rate-based Model

  • Jung, Jongyeon;Seo, Yutaek
    • Journal of Ocean Engineering and Technology
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    • v.36 no.3
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    • pp.168-180
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    • 2022
  • The IMO has decided to proceed with the early introduction of EEDI Phase 3, a CO2 emission regulation to prevent global warming. Measures to reduce CO2 emissions for ships that can be applied immediately are required to achieve CO2 reduction. We set six different CO2 emission scenarios according to the type of ship and fuel, and designed a monoethanolamine-based CO2 capture process for ships using a rate-based model of Aspen Plus v10. The simulation model using Aspen Plus was validated using pilot plant operation data. A ship inevitably tilts during operation, and the performance of a tilted column decreases as its height increases. When configuring the conventional CO2 capture process, we considered that the required column heights were so high that performance degradation was unavoidable when the process was implemented on a ship. We applied a parallel column concept to lower the column height and to enable easy installation and operation on a ship. Simulations of the parallel column confirmed that the required column height was lowered to less than 3 TEU (7.8 m).

The Optimization of Process Allocation for Quality Improvement under Product Liability Environment (제품책임(製品責任) 시대(時代)에 품질향상(品質向上)을 위한 공정개선(工程改善)의 최적화(最適化))

  • Jo, Nam-Ho;Lee, Geun-Hui
    • Journal of Korean Society for Quality Management
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    • v.15 no.2
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    • pp.20-26
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    • 1987
  • An algorithm for the minimum total process percent defective under marginal costs is presented. Initial process is single series system, which is constructed by k process units, and each process is considered priority. Minimum of total process percent defective for parallel-series system exists when additional process setup costs are larger than marginal costs.

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A architecture for parallel rendering processor with by effective memory organization (효과적인 메모리 구조를 갖는 병렬 렌더링 프로세서 구조)

  • Kim, Kyung-Su;Yoon, Duk-Ki;Kim, Il-San;Park, Woo-Chan
    • Journal of Korea Game Society
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    • v.5 no.3
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    • pp.39-47
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    • 2005
  • Current rendering processors are organized mainly to process a triangle as fast as possible and recently parallel 3D rendering processors, which can process multiple triangles in parallel with multiple rasterizers, begin to appear. For high performance in processing triangles, it is desirable for each rasterizer have its own local pixel cache. However, the consistency problem may occur in accessing the data at the same address simulaneously by more than one rasterizer. In this paper, we propose a parallel rendering processor architecture resolving such consistency problem effectively. Moreover, the proposed architecture reduces the latency due to a pixel cache miss significantly. The experimental results show that proposed architecture achieves almost linear speedup at best case even in sixteen rasterizer

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Parallel Computing Based Design Framework for Multidisciplinary Design Optimization (병렬 컴퓨팅 기반 다분야통합최적설계 지원 설계 프레임워크)

  • Chu, Min-Sik;Lee, Yong-Bin;Lee, Se-Jung;Choi, Dong-Hoon
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.33 no.8
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    • pp.34-41
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    • 2005
  • A parallel computing technique was applied to large scale structure analysis or aerodynamic design and it is a essential element in reducing the huge computation time for large scale design problem. We can use a many computers for reducing the analysis time of multidisciplinary design optimization. But previous MDO frameworks can not support a parallel design process technique so still existing which calls an analysis program continuously. In this paper, We developed a MDO framework(MLR) which supports a parallel design process to solve sequential analysis call. Finally, three sample cases are presented to show the efficiency of design time using the suggested MDO framework.

Design of a Parallel Rendering Processor Architecture with Effective Memory System (효과적인 메모리 구조를 갖는 병렬 렌더링 프로세서 설계)

  • Park Woo-Chan;Yoon Duk-Ki;Kim Kyoung-Su
    • The KIPS Transactions:PartA
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    • v.13A no.4 s.101
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    • pp.305-316
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    • 2006
  • Current rendering processors are organized mainly to process a triangle as fast as possible and recently parallel 3D rendering processors, which can process multiple triangles in parallel with multiple rasterizers, begin to appear. For high performance in processing triangles, it is desirable for each rasterizer have its own local pixel cache. However, the consistency problem may occur in accessing the data at the same address simultaneously by more than one rasterizer. In this paper, we propose a parallel rendering processor architecture resolving such consistency problem effectively. Moreover, the proposed architecture reduces the latency due to a pixel cache miss significantly. For the above two goals, effective memory organizations including a new pixel cache architecture are presented. The experimental results show that the proposed architecture achieves almost linear speedup at best case even in sixteen rasterizers.

Parallel Design and Implementation of Shot Boundary Detection Algorithm (샷 경계 탐지 알고리즘의 병렬 설계와 구현)

  • Lee, Joon-Goo;Kim, SeungHyun;You, Byoung-Moon;Hwang, DooSung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.2
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    • pp.76-84
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    • 2014
  • As the number of high-density videos increase, parallel processing approaches are necessary to process a large-scale of video data. When a processing method of video data requires thousands of simple operations, GPU-based parallel processing is preferred to CPU-based parallel processing by way of reducing the time and space complexities of a given computation problem. This paper studies the parallel design and implementation of a shot-boundary detection algorithm. The proposed shot-boundary detection algorithm uses pixel brightness comparisons and global histogram data among the blocks of frames, and the computation of these data is characterized with the high parallelism for the related operations. In order to maximize these operations in parallel, the computations of the pixel brightness and histogram are designed in parallel and implemented in NVIDIA GPU. The GPU-based shot detection method is tested with 10 videos from the set of videos in National Archive of Korea. In experiments, the detection rate is similar but the computation time is about 10 time faster to that of the CPU-based algorithm.

A Parallel Match Method for Path-oriented Query Processing in iW- Databases (XML 데이타베이스에서 경로-지향 질의처리를 위한 병렬 매치 방법)

  • Park Hee-Sook;Cho Woo-Hyun
    • Journal of KIISE:Databases
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    • v.32 no.5
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    • pp.558-566
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    • 2005
  • The XML is the new standard fir data representation and exchange on the Internet. In this paper, we describe a new approach for evaluating a path-oriented query against XML document. In our approach, we propose the Parallel Match Indexing Fabric to speed up evaluation of path-oriented query using path signature and design the parallel match algorithm to perform a match process between a path signature of input query and path signatures of elements stored in the database. To construct a structure of the parallel match indexing, we first make the binary tie for all path signatures on an XML document and then which trie is transformed to the Parallel Match Indexing Fabric. Also we use the Parallel Match Indexing Fabric and a parallel match algorithm for executing a search operation of a path-oriented query. In our proposed approach, Time complexity of the algorithm is proportional to the logarithm of the number of path signatures in the XML document.

Development and Evaluation of Automatic Steering System for Parallel Parking (평행주차를 위한 자동 조향 제어시스템 개발 및 성능평가)

  • Lee, Dae Hyun;Kim, Yong Joo;Kim, Tae Hyeong;Chung, Sun Ok;Choi, Chang Hyun
    • Journal of Drive and Control
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    • v.13 no.1
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    • pp.18-26
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    • 2016
  • This research is conducted to develop an automatic steering system for parallel parking, and the performance of the system was evaluated by parallel parking a conventional vehicle. The automatic steering system consisted of MDPS (motor driven power steering) to control steering, ESC (electronic stability control) to acquire wheel speed, ultrasonic sensors to recognize the parking space, and a controller to communicate and handle data. The parallel parking process using the automatic steering control consisted of parking space recognition, parking path generation, and parking path tracking. The path for parallel parking was generated based on a kinematic model of a conventional vehicle, and a PI controller was used to control the steering angle for path tracking. Parallel parking using the automatic steering control was conducted according to vehicle speed conditions. The results show that the errors on the x-axis and y-axis were below 0.54 m and 0.14 m, respectively, and the error on the steering angle was less than $1^{\circ}$. Therefore, it is possible to implement parallel parking using an automatic steering control system for conventional vehicles.