• 한국태양에너지학회 논문집
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• 제39권1호
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• pp.59-66
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• 2019

BIPV or BAPV installation applied to building is increasing through public utility mandates enterprise. Solar PV energy generates only during the day, but if it is operated in convergence with ESS, which stores electrical energy, it can restrain the fossil energy used in buildings throughout the day. A solution is to converge with PV system and ESS. However, PV systems and ESS connected to the power grid in parallel can cause problems of electrical stability. A study was conducted on the case of failure to detect islanding operation under the parallel operation of PV generation and ESS that are connected in parallel to power grid. Experiments conducted various non-islanding detections under the operating conditions. In the experiment results, when one PCS - PV inverter or ESS inverter - was operating under the islanding condition, it stopped working within 0.5 seconds of the Korean grid standard. However, when both of PV inverter and ESS inverter were operating at the same time under the islanding situation, the anti-islanding algorithm did not operate normally and both inverters continuously supplied power to the connected RLC loads. islanding detection Algorithm developed by each inverter manufacturer has caused this phenomenon. Therefore, this paper presented a new test standard for islanding detection.

• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.2224-2236
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• 2014

The performance of an isolated high voltage full bridge converter is improved using a voltage doubler. In a conventional high voltage full bridge converter, the diode of the transformer secondary voltage undergoes a voltage spike due to the leakage inductance of the transformer and the resonance occurring with the parasitic capacitance of the diode. In addition, in the phase shift control, conduction loss largely increases from the freewheeling mode because of the circulating current. The efficiency of the converter is thus reduced. However, in the proposed converter, the high voltage dual converter consists of a voltage doubler because the circulating current of the converter is reduced to increase efficiency. On the other hand, in the proposed converter, an input current is distributed when using parallel input / serial output and the output voltage can be doubled. However, the voltages in the 2 serial DC links might be unbalanced due to line impedance, passive and active components impedance, and sensor error. Considering these problems, DC injection is performed due to the complementary operations of half bridge inverters as well as the disadvantage of the unbalance in the DC link. Therefore, the serial output of the converter needs to control the balance of the algorithm. In this paper, the performance of the conventional converter is improved and a balance control algorithm is proposed for the proposed converter. Also, the system of the 1.5[kW] PCS is verified through an experiment examining the operation and stability.

• 전력전자학회논문지
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• 제18권2호
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• pp.131-137
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• 2013

In this paper, the phase-shift full-bridge DC/DC converter with fixed-phase operation inverter is proposed. The proposed circuit consists of two full-bridge inverters which are connected in parallel. While one full-bridge inverter operates as the fixed-phase, it regulates the output voltage by adjusting the phase of the other inverter. During the normal operation period, the proposed circuit makes the less amount of conduction loss of the primary switches and secondary synchronous rectifiers, as well as the less amount of the current ripple of the output inductor, than the conventional phase-shift full-bridge DC/DC converter does. Also, it achieves high efficiency by reducing the snubber loss of the secondary synchronous rectifier. To sum up, the present inquiry analyzes the theoretical characteristics of the proposed circuit, and shows the experimental results from a prototype for 450W power supply.

• 대한전자공학회논문지SD
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• 제38권7호
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• pp.493-502
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• 2001

기존의 논리 테스팅에 비하여 여러 가지 장점을 가지는 전류 테스팅을 위하여 새로운 내장형 전류 감지 회로를 설계하였다. 본 논문에서 제안된 내장형 전류 감지 회로는 시험 대상 회로에서 발생하는 전류와 인버터의 전류 발생 특성에 의해 복사되어진 전류를 비교함으로서 시험 대상 회로의 고장 존재 여부를 감지하여 Pass/Fail 신호로 발생시킨다. 설계된 회로는 차동 증폭 형태의 증폭기와 비교기로 이루어져 있으며, 시험 대상 회로의 전류를 복사해 내기 위한 인버터를 포함하고 있어서 총 10개의 트랜지스터와 3개의 인버터를 사용한다. 본 논문에서 제안된 내장형 전류 감지 회로는 고장 테스트를 위하여 별도의 클럭을 사용하지 않는다. 또한 모드 선택이 필요하지 않아 on-line 테스팅이 가능하며, Pass/Fail 신호를 칩의 외부로 전달하는 출력단자 하나를 제외하고는 별도의 제어단자가 필요하지 않은 장점을 가진다. HSPICE를 사용한 컴퓨터 모의 실험을 통하여 시험 대상 회로에 삽입된 고장을 정확하게 검출해 낼 수 있음을 확인하였다. 제안된 내장형 전류 감지 회로가 칩의 전체 면적에서 차지하는 면적소모는 8×8 병렬 승산기를 시험 대상 회로로 사용한 경우에 약 4.34 %로 매우 작아서 내장형 전류 감지회로에 의한 면적 소모에 대한 부담은 거의 없는 것으로 측정되었다.