• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.981-984
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• 1993

During the past decade, several specific hardwares for fast fuzzy inference have been developed. Most of them are dedicated to a specific inference method and thus cannot support other inference methods. In this paper, we present a hardware architecture called KAFA(KAist Fuzzy Accelerator) which provides various fuzzy inference methods and fuzzy set operators. The architecture has SIMD structure, which consists of two parts; system control/interface unit(Main Controller) and arithmetic units(FPEs). Using the parallel processing technology, the KAFA has the high performance for fuzzy information processing. The speed of the KAFA holds promise for the development of the new fuzzy application systems.

• Journal of the Korean Institute of Intelligent Systems
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• v.2 no.2
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• pp.34-41
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• 1992

A robust and reliable learning and reasoning mechanism is addressed based upon fuzzy set theory and fuzzy associative memories. The mechanism stores a priori an initial knowledge base via approximate learning and utilizes this information for decision-making systems via fuzzy inferencing. We called this fuzzy computer architecture a 'fuzzy hypercube' processing all the rules in one clock period in parallel. Fuzzy hypercubes can be applied to control of a class of complex and highly nonlinear systems which suffer from vagueness uncertainty. Moreover, evidential aspects of a fuzzy hypercube are treated to assess the degree of certainty or reliability together with parameter sensitivity.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.1386-1389
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• 1993

We are describing the architecture of a fuzzy logic controller using pulse-width-modulation (PDM) technique and a pipeline structure. Features of this controller are: A new architecture for the inference unit, reduced chip area and less I/O-pins. Additionally we present two different rule-bases: one hardwired with reduced chip-area and the other programmable for prototyping. Also an architecture of a parallel minimum-gate is shown.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.4 no.6
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• pp.1294-1310
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• 2010

User authentication using fingerprint information provides convenience as well as strong security. However, serious problems may occur if fingerprint information stored for user authentication is used illegally by a different person since it cannot be changed freely as a password due to a limited number of fingers. Recently, research in fuzzy fingerprint vault system has been carried out actively to safely protect fingerprint information in a fingerprint authentication system. In addition, research to solve the fingerprint alignment problem by applying a geometric hashing technique has also been carried out. In this paper, we propose the hardware architecture for a geometric hashing based fuzzy fingerprint vault system that consists of the software module and hardware module. The hardware module performs the matching for the transformed minutiae in the enrollment hash table and verification hash table. On the other hand, the software module is responsible for hardware feature extraction. We also propose the hardware architecture which parallel processing technique is applied for high speed processing. Based on the experimental results, we confirmed that execution time for the proposed hardware architecture was 0.24 second when number of real minutiae was 36 and number of chaff minutiae was 200, whereas that of the software solution was 1.13 second. For the same condition, execution time of the hardware architecture which parallel processing technique was applied was 0.01 second. Note that the proposed hardware architecture can achieve a speed-up of close to 100 times compared to a software based solution.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.18 no.2
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• pp.284-310
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• 2024

Identifying clinical pathways for disease diagnosis and treatment process recommendations are seriously decision-intensive tasks for health care practitioners. It requires them to rely on their expertise and experience to analyze various categories of health parameters from a health record to arrive at a decision in order to provide an accurate diagnosis and treatment recommendations to the end user (patient). Technological adaptation in the area of medical diagnosis using AI is dispensable; using expert systems to assist health care practitioners in decision-making is becoming increasingly popular. Our work architects a novel knowledge-based recommender system model, an expert system that can bring adaptability and transparency in usage, provide in-depth analysis of a patient's medical record, and prescribe diagnostic results and treatment process recommendations to them. The proposed system uses a set of parallel discrete fuzzy rule-based classifier systems, with each of them providing recommended sub-outcomes of discrete medical conditions. A novel knowledge-based combiner unit extracts significant relationships between the sub-outcomes of discrete fuzzy rule-based classifier systems to provide holistic outcomes and solutions for clinical decision support. The work establishes a model to address disease diagnosis and treatment recommendations for primary lung disease issues. In this paper, we provide some samples to demonstrate the usage of the system, and the results from the system show excellent correlation with expert assessments.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1998.06a
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• pp.459-464
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• 1998

In this paper, we propose a stable fuzzy logic controller architecture for inverted pendulum,. In the design procedure, we represent the fuzzy system as a Takagi-Sugeno fuzzy model and construct a global fuzzy logic controller by considering each local state feedback controller and a supervisory controller, Unlike usual parallel distributed controller, one can design a global stable fuzzy controller without finding a common Lyapunov function by the proposed method. A simulation is performed to control the inverted pendulum to show the effectiveness and feasibility of the proposed fuzzy controller.

• The KIPS Transactions:PartA
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• v.16A no.6
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• pp.411-418
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• 2009

Vector quantization algorithm based on fuzzy clustering has been widely used in the field of data compression since the use of fuzzy clustering analysis in the early stages of a vector quantization process can make this process less sensitive to its initialization. However, the process of fuzzy clustering is computationally very intensive because of its complex framework for the quantitative formulation of the uncertainty involved in the training vector space. To overcome the computational burden of the process, this paper introduces an array architecture for the implementation of fuzzy vector quantization (FVQ). The arrayarchitecture, which consists of 4,096 processing elements (PEs), provides a computationally efficient solution by employing an effective vector assignment strategy during the clustering process. Experimental results indicatethat the proposed parallel implementation providessignificantly greater performance and efficiency than appropriately scaled alternative array systems. In addition, the proposed parallel implementation provides 1000x greater performance and 100x higher energy efficiency than other implementations using today's ARMand TI DSP processors in the same 130nm technology. These results demonstrate that the proposed parallel implementation shows the potential for improved performance and energy efficiency.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Journal of the Korean Institute of Intelligent Systems
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• v.5 no.4
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• pp.77-86
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• 1995

The new architecture that fuzzy logic control(FLC) with difficulties for tuning membership function (MF) is parallel with neural networks(NN) to be learned from the output of FLC is proposed. Therefore proposed scheme has the characteristics to utilize the expert knowledge in design process, to be learned during the operation without any learning mode. In this architecture, the function of the FLC is to supply the sliding surface which is constructed on the phase plane by rule base for giving the desired control characteristics and learning criterion of NN and the stabilization of the control performance before NN is learned, The function of the NN is to let the system trajectory be tracked to the sliding surface and reached to the stable point.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.7 no.3
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• pp.176-181
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• 2007

This paper presents evolvable neural networks based on a developmental model for navigation control of autonomous mobile robots in dynamic operating environments. Bio-inspired mechanisms have been applied to autonomous design of artificial neural networks for solving practical problems. The proposed neural network architecture is grown from an initial developmental model by a set of production rules of the L-system that are represented by the DNA coding. The L-system is based on parallel rewriting mechanism motivated by the growth models of plants. DNA coding gives an effective method of expressing general production rules. Experiments show that the evolvable neural network designed by the production rules of the L-system develops into a controller for mobile robot navigation to avoid collisions with the obstacles.