• Journal of IKEEE
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• v.24 no.2
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• pp.649-653
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• 2020

GPS is a representative satellite navigation system that provides users with accurate location and time information. GPS L1 C / A is opened for civilian and thus utilized in various fields. When the satellite signal reaches the receiver, signal acquisition unit of the digital signal processing hardware searches and acquires the signal among visible satellites. The signal acquisition unit has different implementation methods depending on the signal searching method, such as serial search acquisition, parallel frequency search, parallel code phase search. In this paper, we compare and analyze the three representative acquisition hardwares using live GPS L1 C/A signals. According to the comparison, the parallel code phase search acquisition outperforms the other methods due to reduction of the number of the searchings and a high resolution.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.7
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• pp.1716-1725
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• 1996

In this paper, the huffman decoder which is a part of the decoder in JPEG standard format is designed by using a new Ternary CAM. First, the 256 word * 16 bit-size new bit-word all parallel Ternary CAM system is designed and verified using SPICE and CADENCE Verilog-XL, and then the verified novel Ternary CAM is applied to the new huffman decoder architecture of JPEG. So the performnce of the designed CAM cell and it's block is verified. The new Ternary CAM has various applications because it has search data mask and storing data mask function, which enable bit-wise search and don't care state storing. When the CAM is used for huffman look-up table in huffman decoder, the CAM is partitioned according to the decoding symbol frequency. The scheme of partitioning CAM for huffman table overcomes the drawbacks of all-parallel CAM with much power and load. So operation speed and power consumption are improved.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.405-414
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• 2016

IC-implementations provide high performance for solving the high computational cost of pattern matching but have relative low flexibility for satisfying different applications. In this paper, we report an associative memory architecture for k nearest neighbor (KNN) search, which is one of the most basic algorithms in pattern matching. The designed architecture features reconfigurable vector-component parallelism enabled by programmable switching circuits between vector components, and a dedicated majority vote circuit. In addition, the main time-consuming part of KNN is solved by a clock mapping concept based weighted frequency dividers that drastically reduce the in principle exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. A test chip in 180 nm CMOS technology, which has 32 rows, 8 parallel 8-bit vector-components in each row, consumes altogether in peak 61.4 mW and only 11.9 mW for nearest squared Euclidean distance search (at 45.58 MHz and 1.8 V).

• Journal of the Ergonomics Society of Korea
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• v.28 no.4
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• pp.91-99
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• 2009

A visual stress may provoke migraine, cephalalgia, intervene a long term reading and learning capability and reduce the productivity of a laborer who uses computer for a good while. In this study, a web based screening tool for visual stress was developed, it applied to 72 visually normal young persons in parallel with traditional questionnaire about symptoms of visual stress. To estimate visual stress, It is proposed to measure difference of visual search time of Han Gul characters as targets between visual stressful pattern and non-visual stressful pattern as global background of characters. As a result of test, 5 subjects were screened whose mean visual search time in the stressful pattern with 6 CPD spatial frequency increase significantly more than in none stressful pattern(t-test, one-tailed, p=$1.0407\times10^{-11}$). 2 of them were diagnosed as mild visual stress syndrome in the clinic. None had visual distortion and 50% of subjects had visual discomfort in results of the questionnaire. Correlation between visual search time increase rate and normalized number of visual discomfort may be slight(C. coefficient=0.1355). This study may contribute as a basic research for screening person with migraine, visual reading disabilities and VDT syndrome. It is required to apply the test to visual reading disabilities, migraine with visual distortion and/or visual discomfort as well as normal person for higher reliability of the screening tool.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.8
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• pp.54-65
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• 1992

A huge amount of multiplications is required for 2-D filtering on the image data, making it difficult to implement a real-time quincuncial interpolator. In this paper, efficient design technique and VLSI structures for 2-D multipleierless filter are presented. In the filter design, by introducing an efficient scheme for discretizing the frequency response of the prototype filter, it is shown that a significant amount of the computational burden required in the conventional techniques, such as local search, branch and bound techniques, could be saved. In the case of 5$\times$5 filter, it is found that the design technique described in this paper could save about 80% of the computation time, compared to the conventional methods, while providing a comparable performance. For a hardware implementation, two different VLSI structures for 2-D multiplierless filter are also introduced in the paper : One is for block parallel processing and the other for scan-line parallel processing. In both structure, the AP(area-period) figure improves over Wu's structure[4].

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.9
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• pp.76-84
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• 1994

This paper presents a new high-performance VLSI architecture and VLSI implementation for full-search block matching algorithm. The proposed VLSI architecture has the feature of two directional parallel and pipeline processing, thereby reducing the PE idle time at which the direction of block matching operation within the search area is changed. Therfore, the proposed architecture is faster than the existing architectures under the same clock frequency. Based on HSPICE circuit simulation, it is verified that the implemented procesing element is operated successfully within 13 ns for 75 MHz operation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.37-44
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• 2010

New features of motion compensation, such as variable block size and multiple reference frames are introduced in H.264/AVC. However, these new features induce significant implementation complexity increases. In this paper, an efficient architecture for spiral-type motion estimation is proposed. First, we propose a hardware-friendly spiral search order. Then, an efficient processing element (PE) architecture for ME is proposed to achieve the proposed search order. The improved PE enables one-pixel-move of the reference pixel data to top, bottom, right, and left by four ports for input and output. Moreover, the parallel calculation architecture to calculate all block size with the SAD of 4x4 is introduced in the proposed architecture. As the result of hardware implementation, the hardware cost is about 145k gates. Maximum clock frequency is 134 MHz in the case of FPGA (Xilinx Vertex5) implementation.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.7
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• pp.2879-2890
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• 2020

In this paper, we study the estimation of angle, range and polarization parameters of a bistatic polarization sensitive frequency diverse array multiple-input multiple-output (PSFDA-MIMO) radar system. The application of polarization sensitive array in receiver is explored. A signal model of bistatic PSFDA-MIMO radar system is established. In order to utilize the multi-dimensional structure of array signals, the matched filtering radar data can be represented by a third-order tensor model. A joint estimation of the direction-of-departure (DOD), direction-of-arrival (DOA), range and polarization parameters based on parallel factor (PARAFAC) algorithm is proposed. The proposed algorithm does not need to search spectral peaks and singular value decomposition, and can obtain automatic pairing estimation. The method was compared with the existing methods, and the results show that the performance of the method is better. Therefore, the accuracy of the parameter estimation is further improved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.58-65
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and variable point 2D SAD hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the SAD unit and its parallel operations using pattern information, the proposed IME instructions support not only full search algorithms but also other fast search algorithms. The hardware size is 25.5K gates for each Processing Element Group (PEG) which has 128 SAD Processor Elements (PEs). The proposed ASIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The hardware size is 453K gates for the IME unit and the operating frequency is 188MHz for 1080p@30 frame in real time. The proposed ASIP can reduce the hardware size about 26% and the number of operation cycles about 18%.

• Journal of Internet Computing and Services
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• v.15 no.2
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• pp.19-31
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• 2014

In this paper, a parallel backoff delay procedure on multiple IEEE 802.15.4 channels and a channel searching method considering the frequency spectrum of WiFi traffic are studied for IEEE 802.15.4 nodes to avoid the interference from WiFi traffic. In order to search the channels being occupied by WiFi traffic, we analyzed the methods measuring the powers of adjacent channels simultaneously, checking the duration of measured power levels greater than a threshold, and finding the same periodicity of sampled RSSI data as the beacon frame by signal processing. In an wireless channel overlapped with IEEE 802.11 network, the operation of CSMA-CA algorithm for IEEE 802.15.4 nodes is explained. A method to execute a parallel backoff procedure on multiples IEEE 802.15.4 channels by an IEEE 802.15.4 device is proposed with the description of its algorithm. When we analyze the data measured by the experimental system implemented with the proposed method, it is observed that medium access delay times increase at the same time in the associated IEEE 802.15.4 channels that are adjacent each other during the generation of WiFi traffic. A channel evaluation function to decide the interference from other traffic on an IEEE 802.15.4 channel is defined. A channel searching method considering the channel evaluations on the adjacent channels together is proposed in order to search the IEEE 802.15.4 channels interfered by WiFi, and the experimental results show that it correctly finds the channels interfered by WiFi traffic.