• 제목/요약/키워드: Parallel device

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An Improvement Parallel to the Efficiency of Boost Converter for Power Factor Correction (PFC용 부스트 컨버터의 병렬화에 의한 효율 개선)

  • 전내석;장수형;전일영;박영산;안병원;이성근;김윤식
    • Proceedings of the Korean Society of Marine Engineers Conference
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    • 2001.11a
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    • pp.120-124
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    • 2001
  • A new technique for improving the efficiency of single-phase high-frequency boost converter is proposed. This converter includes an additional low-frequency boost converter which is connected to the main high-frequency switching device in parallel. The additional converter is controlled at lower frequency. Most of the current flows in the low-frequency switch and so, high-frequency switching loss is greatly reduced accordingly Both switching device are controlled by a simple method; each controller consists of a one-shot multivibrator, a comparator and an AND gate. The converter works cooperatively in high efficiency and acts as if it were a conventional high-frequency boost converter with one switching device. The proposed method is verified by simulation. This paper describes the converter configuration and design, and discusses the steady-state performance concerning the switching loss reduction and efficiency improvement.

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Configuration System Implementation Algorithm to Manage the I/O Device of the Parallel Processing Programmable Logic Controller (병렬 처리 기법을 이용한 프로그래머블 로직 컨트롤러의 입출력 접점 관리를 위한 컨피규레이션 시스템 구현 알고리즘)

  • Kim, Kwang-Jin;Kwon, Wook-Hyun
    • Proceedings of the KIEE Conference
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    • 1998.07g
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    • pp.2327-2329
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    • 1998
  • In this paper, an algorithm to make a configuration system for managing the I/O device of programmable logic controller(PLC) is proposed. Parallel processing architecture is used to deal with a number of I/O devices. From that architecture, a contention problem between processors can arise. To resolve this problem, the configuration system that contains informations about I/O devices is introduced. This configuration system is used to check the contention between processors in the I/O device and also used in program execution.

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Kinematical Characteristics of Vibration Assisted Cutting Device Constructed with Parallel Piezoelectric Stacked Actuators (평행한 적층 압전 액추에이터로 구성된 진동절삭기의 기구학적 특성 고찰)

  • Loh, Byoung-Gook;Kim, Gi-Dae
    • Transactions of the Korean Society for Noise and Vibration Engineering
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    • v.21 no.12
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    • pp.1185-1191
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    • 2011
  • The kinematic characteristics of cutting device significantly affects cutting performance in 2-dimensional elliptical vibration cutting(EVC) where the cutting tool cuts workpiece, traversing a micro-scale elliptical trajectory in a trochoidal motion. In this study, kinematical characteristics of EVC device constructed with two parallel stacked piezoelectric actuators were analytically modeled and compared with the experimental results. The EVC device was subjected to step and low-frequency(0.1 Hz) sinusoidal inputs to reveal only its kinematical displacement characteristics. Hysteresis in the motion of the device was observed in the thrust direction and distinctive skew of the major axis of the elliptical trajectory of the cutting tool was also noticed. Discrepancy in the voltage-to-displacement characteristics of the piezoelectric actuators was found to largely contribute to the skew of the major axis of the elliptical trajectory of the cutting tool. Analytical kinematical model predicted the cutting direction displacement within 10 % error in magnitude with no phase error, but in estimating the thrust direction displacement, it showed a $27^{\circ}$ of phase-lag compared with the measured displacement with no magnitude error.

A Study on ESD Protection Circuit with High Holding Voltage with Parallel PNP and N+ difrt inserted (Parallel PNP 및 N+ drift가 삽입된 높은 홀딩전압특성을 갖는 ESD보호회로에 관한 연구)

  • Kwak, Jae-Chang
    • Journal of IKEEE
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    • v.24 no.3
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    • pp.890-894
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    • 2020
  • In this paper, we propose an ESD protection device with improved electrical characteristics through structural changes of LVTSCR, a typical ESD protection device. The proposed ESD protection device has a higher holding voltage than the existing LVTSCR by inserting a long N+ drift region and additional P-Well and N-Well, and improves the latch-up immunity, a chronic disadvantage of a general SCR-based ESD protection device. In addition, the effective base width of parasitic BJTs was set as a design variable, and the electrical characteristics of the proposed ESD protection device were verified through Synopsys' TCAD simulation so that it can be applied to the required application by applying the N-Stack technology.

Design and Implementation of Algorithms for the Motion Detection of Vehicles using Hierarchical Motion Estimation and Parallel Processing (계층화 모션 추정법과 병렬처리를 이용한 차량 움직임 측정 알고리즘 개발 및 구현)

  • 강경훈;정성태;이상설;남궁문
    • Journal of Korea Multimedia Society
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    • v.6 no.7
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    • pp.1189-1199
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    • 2003
  • This paper presents a new method for the motion detection of vehicles using hierarchical motion estimation and parallel processing. It captures the road image by using a CMOS sensor. It divides the captured image into small blocks and detects the motion of each block by using a block-matching method which is based on a hierarchical motion estimation and parallel processing for the real-time processing. The parallelism is achieved by using tile pipeline and the data flow technique. The proposed method has been implemented by using an embedded system. The proposed block matching algorithm has been implemented on PLDs(Programmable Logic Device) and clustering algorithm has been implemented by ARM processor. Experimental results show that the proposed system detects the motion of vehicles in real-time.

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The control & measurement of DC/STEP motor device using the computer (PC를 이용한 직류/스탭모터 장치의 제어.계측)

  • Son, Jun-Hyug;Seo, Bo-Hyeok
    • Proceedings of the KIEE Conference
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    • 2002.07d
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    • pp.2206-2208
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    • 2002
  • In this paper, using the communication port between PC(Personal Computer) and DC/STEP MOTOR DEVICE that movement and measurement of motor. Communication port used serial port and movement order transmits by communication port. Consequence of motor device movement displays to tile DC/STEP MOTOR DEVICE APPLICATION. This connection is using the serial port instead of parallel port faster than response time And this application is easier than existing application.

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A Study on the Test Strategy of Digital Circuit Board in the Production Line Based on Parallel Signature Analysis Technique (PSA 기법에 근거한 생산라인상의 디지털 회로 보오드 검사전략에 대한 연구)

  • Ko Yun-Seok
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.53 no.11
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    • pp.768-775
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    • 2004
  • The SSA technique in the digital circuit test is required to be repeated the input pattern stream to n bits output nodes n times in case of using a multiplexor. Because the method adopting a parallel/serial bit convertor to remove this inefficiency has disadvantage of requiring the test time n times for a pattern, the test strategy is required, which can enhance the test productivity by reducing the test time based on simplified fault detection mechanism. Accordingly, this paper proposes a test strategy which enhances the test productivity and efficiency by appling PAS (Parallel Signature Analysis) technique to those after analyzing the structure and characteristics of the digital devices including TTL and CMOS family ICs as well as ROM and RAM. The PSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Resister) representing the characteristic equation. Also, the method to obtain the optimal signature analyzer is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

Compensating the Elliptical Trajectory of Elliptical Vibration Cutting Device (타원궤적 진동절삭기의 타원궤적 보정)

  • Loh, Byoung-Gook;Kim, Gi-Dae
    • Journal of the Korean Society for Precision Engineering
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    • v.28 no.7
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    • pp.789-795
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    • 2011
  • In elliptical vibration cutting (EVC), cutting performance is largely affected by the shape of an elliptical path of the cutting tool. In this study, two parallel piezoelectric actuators were used to make an elliptical vibration cutting device. When harmonic voltages of $90^{\circ}$ out-of-phase are supplied to the EVC device, creation of an ideal elliptical trajectory whose major and minor axes are parallel to the cutting and thrust directions is anticipated from a kinematic analysis of the EVC device, however, the paths we experimentally observed showed significant distortions in its shape ranging from skew to excessive elongation of the major axis of the ellipse. To compensate distortions, an analytical model describing the elliptical path of the cutting tool was developed and verified with experimental results, and based on the analytical model, the distorted elliptical paths created at 100 Hz, 1 kHz, and 16 kHz were corrected for skew and elongation.

Influence of Device Parameters Spread on Current Distribution of Paralleled Silicon Carbide MOSFETs

  • Ke, Junji;Zhao, Zhibin;Sun, Peng;Huang, Huazhen;Abuogo, James;Cui, Xiang
    • Journal of Power Electronics
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    • v.19 no.4
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    • pp.1054-1067
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    • 2019
  • This paper systematically investigates the influence of device parameters spread on the current distribution of paralleled silicon carbide (SiC) MOSFETs. First, a variation coefficient is introduced and used as the evaluating norm for the parameters spread. Then a sample of 30 SiC MOSFET devices from the same batch of a well-known company is selected and tested under the same conditions as those on datasheet. It is found that there is big difference among parameters spread. Furthermore, comprehensive theoretical and simulation analyses are carried out to study the sensitivity of the current imbalance to variations of the device parameters. Based on the concept of the control variable method, the influence of each device parameter on the steady-state and transient current distributions of paralleled SiC MOSFETs are verified separately by experiments. Finally, some screening suggestions of devices or chips before parallel-connection are provided in terms of different applications and different driver configurations.