• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1083-1086
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• 2000

In this paper a development of 10KVA series-parallel compensated UPS is shown, which has high input power factor and sinusoidal output voltage regulation capability. Compared to conventional cascaded UPS, the size can be reduced significantly with high quality input and output waveforms. The front converter and the main inverter can be considered decoupled, hence the front converter and the main inverter can be designed independent of each other. In this paper, analysis and experimental results for an 10 KVA prototype are presented.

• Journal of Power Electronics
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• v.10 no.1
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• pp.9-13
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• 2010

This paper proposes an input-series-output-parallel connected ZVS full bridge converter with interleaved control for photovoltaic power conditioning systems (PV PCS). The input-series connection enables a fully modular power-system architecture, where low voltage and standard power modules can be connected in any combination at the input and/or at the output, to realize any given specifications. Further, the input-series connection enables the use of low-voltage MOSFETs that are optimized for a very low RDSON, thus, resulting in lower conduction losses. The system costs decrease due to the reduced current, and the volumes of the output filters due to the interleaving technique. A topology for a photovoltaic (PV) dc/dc converter that can dramatically reduce the power rating and increase the efficiency of a PV system by analyzing the PV module characteristics is proposed. The control scheme, consisting of an output voltage loop, a current loop and input voltage balancing loops, is proposed to achieve input voltage sharing and output current sharing. The total PV system is implemented for a 10-kW PV power conditioning system (PCS). This system has a dc/dc converter with a 3.6-kW power rating. It is only one-third of the total PV PCS power. A 3.6-kW prototype PV dc/dc converter is introduced to experimentally verify the proposed topology. In addition, experimental results show that the proposed topology exhibits good performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.1-7
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• 2009

This paper describes design of high energy efficiency 32 bit parallel processor core using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.12
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• pp.95-100
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• 2008

Conventional Earth Leakage Circuit Breakers (ELCBs) have defects of a breaking failure or a long breaking-time against parallel arc current. In this paper, breaking characteristics of conventional ELCBs were analyzed by simulation of parallel arc in a low-voltage indoor wiring system, and an air-core current sensor and a signal converter being most available for parallel arc detection were developed and applied to a conventional ELCB. The proposed tripped the ELCB regardless of the location of parallel arc. The breaking-time was in ranges of $1.74{\sim}8.3[ms]$ depending on the phase of arc generation, which is about 5 times as fast as conventional ELCBs with the breaking-time of 50[ms].

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.69-72
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• 2003

In this paper new control strategy of series resonant converter system for control power supply is suggested. Frequency controlled series resonant converter system is robust to load variations because it is POSR(parallel output series resonant) type. And it provides stable output voltage by changing switching frequency to input voltage variations. Firstly, operation analysis about suggested series resonant converter system was carried. Then simulations using ACSL(Advanced Continuous Simulation Language) and experiments to actual system were carried to prove characteristics of suggested system.

• ETRI Journal
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• v.31 no.3
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• pp.298-303
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• 2009

A single-switch parallel resonant converter for induction heating is implemented. The circuit consists of an input LC-filter, a bridge rectifier, and a controlled power switch. The switch operates in soft commutation mode and serves as a high frequency generator. The output power is controlled via the switching frequency. A steady state analysis of the converter operation is presented. A closed-loop circuit model is also presented, and the experimental results are compared with the simulation results.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.358-361
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• 1999

In auxiliary block of high speed train power factor correction and harmonics reduction is very important issue for efficient energy transport. The GTO-equipped PWM converter is used for traction untill resently. But the rising power capability of IGBTs resently allows to build IGBT-equipped PWM converter with a considerably increased switching frequency. This paper presents switching pattern, control method, operation mode and tuned filter to reduce dc link voltage ripple for paralleled converter.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1019-1022
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• 2003

This paper has proposed a 4- bit 20MHz Flash A/D converter design available analog signal processing and realized its intergrated circuit. The parallel comparison method A/D converter quantized analog signals swiftly using various converters. Also this theme has designed economic power dissipation circuit using a preamplifier of low volt & power CMOS comparator. Also the system was fabricated by Hynix 0.35um CMOS process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.1
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• pp.68-75
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• 2012

This paper presents a comparative analysis of the parallel operation of different switches in a DC/DC converter. In high power applications, multi-switch PWM power conditioners may be preferred despite a higher component count, due to the absence of low frequency filters, reduced switching losses and fault tolerance. The paper demonstrates how current sharing (CSH) and time sharing (TSH) lead to the reduction of switching stress in the parallel operation of switches in any converter. The solutions proposed in this study can be applied on different scales to other power conditioners for DC/DC converter systems. Discussions of the concepts, hypotheses and computer simulations are verified by 1 kW experimental results.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.3
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• pp.538-543
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• 2011

In this paper, design and control of an interleaved boost converter for multi-string PV Inverter are discussed. Interleaved Boost converter can reduce current ripples at input and output side by cancelling an each phase of inductor currents. Therefore, it contributes to increase efficiency and downsize the whole system volume, cost. One of the advantages of the multi-string system is easy to expand power capacity by connecting the converter modules in parallel. In order to reduce current ripples, the inductor currents on each phase are controlled independently in the converter module, and communication between the converter modules is required for further ripple current reduction. Current control algorithm for the balance of the each phase ripple currents and synchronization of the converter modules based on communication are proposed and implemented in the DSP programming. 10kW prototype of the multi-string converter module is assembled and experimental results are presented to verify the proposed ripple current reduction methods.