• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 전력전자학술대회 논문집
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• pp.405-408
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• 1998

In this paper, a predictive current control of 12-pulse parallel connected dual converter system with interphase transfromer(IPT) is presented. Firstly, 12-pulse parallel connected dual converter system and the predictive current control of this system is discussed. And the validity of the presented system and the excellence of the predictive current control response is proved through the simyulation and experiment result.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제49권7호
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• pp.488-493
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• 2000

In this paper, a predictive current control of 12-pulse parallel connected dual converter system without interphase reactors(IPR) is presented. Firstly, the characteristics of system without IPR are analyzed and compared with that of system with IPR. And the predictive current control of this system is discussed. Finally the validity of the presented system and the excellence of the predictive current control response is proved through the simulation results and experimental results.

• 전기학회논문지
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• 제66권2호
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• pp.459-467
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• 2017

An urban railway power substation consists of three thyristor dual converters. Two converters are connected to up and down trolley line to supply the electric energy or feed the regenerative energy back to the distribution. When the two converters break down, the remaining converter is used in an emergency. One thyristor dual converter system (TDCS) manages the energy of two or three railway stations. If the TDCS fails, the trains stop operating. To solve the problem, this paper proposes the three parallel operation control algorithm of thyristor dual converter system using the emergency converter. The broken TDCS can be replaced by the emergency converter in other TDCS. The effectiveness of this proposed control is verified by simulation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 A
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• pp.482-485
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• 1996

In this paper, a predictive current control of 12-pulse parallel connected dual converter system without interphase reactors(IPR) is presented. Firstly, the characteristics of system without IPR are analyzed and compared with that of system with IPR. And the predictive current control of this system is discussed. Finally the validity of the presented system and the excellence of the predictive current control response is proved through the simulation results.

• 전력전자학회논문지
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• 제21권6호
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• pp.473-480
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• 2016

This study proposes a performance improvement for parallel-connected thyristor dual converters using a circulating current with an unbalanced parallel operation compensator. The proposed control method determines a variable reference value for the voltage PI controller according to voltage error at firing angle control applied to a difference current control. This method uses circulating current control to maintain a stable voltage and excellent current response during parallel operation. The effectiveness of the proposed control is verified with a simulation and an experiment based on the comparison of the performance of the proposed control method with other conventional methods.

• Journal of Electrical Engineering and Technology
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• 제11권1호
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• pp.143-149
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• 2016

The two-stage converter is widely used in traditional DC/AC inverter. It has several disadvantages such as complex topology, large volume and high loss. In order to overcome these shortcomings, a novel half load-cycle worked dual SEPIC single-stage inverter, which is based on the analysis of the relationship between input and output voltages of SEPIC converters operating in the discontinuous conduction mode (DCM), is presented in this paper. The traditional single-stage inverter has remarkable advantages in small and medium power applications, but it can’t realize boost DC/AC output directly. Besides one pre-boost DC/DC converter is needed between the DC source and the traditional single-stage inverter. A novel DC/AC inverter without pre-boost DC/DC converter, which is comprised of two SEPIC converters, is studied. The output of dual SEPIC converters is connected with anti-parallel and half load-cycle control is used to realize boost and buck DC/AC output directly and work properly, whatever the DC input voltage is higher or lower than the AC output voltage. The working principle, parameter selection and the control strategy of the inverters are analyzed in this paper. Simulation and experiment results verify the feasibility of the new inverter.

• 조명전기설비학회논문지
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• 제24권9호
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• pp.79-84
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• 2010

This paper discusses the control of generator field using dual IGBT PWM regeneration method to target brushless synchronous generator. If one of PWM bridges happens to fault, it transfers automatically and can be in charge of full load. Also it has an advantage of the operation which UPS connected in parallel with PWM bridge can supply power to excitation system in condition of main power loss. This PWM system supplies field current to generator in one quadrature operation, regenerates field coil energy to main power supplier in four quadrature operation. We designed, manufactured and applied the first trial product at J-power plant.

• 전력전자학회논문지
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• 제22권4호
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• pp.336-344
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• 2017

This paper presents the three-port DC-DC converter modeling and controller design procedure, which is part of the solid-state transformer (SST) to interface medium voltage AC grid to bipolar DC distribution network. Due to the high primary side DC link voltage, the proposed converter employs the three-level neutral point clamped (NPC) topology at the primary side and 2-two level half bridge circuits for each DC distribution network. For the proposed converter particular structure, this paper conducts modeling the three winding transformer and the power transfer between each port. A decoupling method is adopted to simplify the power transfer model. The voltage controller design procedure is presented. In addition, the output current sharing controller is employed for current balancing between the parallel-connected secondary output ports. The proposed circuit and controller performance are verified by experimental results using a 30 kW prototype SST system.

• ETRI Journal
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• 제27권1호
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• pp.81-88
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• 2005

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.